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Message-ID: <CACRpkdYeE9piO=sfdBdq-Wd9uQpxyAb6xWYJ+9-JMTjrWX9pXw@mail.gmail.com>
Date: Tue, 7 Sep 2021 22:53:08 +0200
From: Linus Walleij <linus.walleij@...aro.org>
To: Wenbin Mei <wenbin.mei@...iatek.com>
Cc: Ulf Hansson <ulf.hansson@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Chaotian Jing <chaotian.jing@...iatek.com>,
Avri Altman <avri.altman@....com>,
Wolfram Sang <wsa+renesas@...g-engineering.com>,
Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>,
Yue Hu <huyue2@...ong.com>,
Adrian Hunter <adrian.hunter@...el.com>,
Bean Huo <beanhuo@...ron.com>,
linux-mmc <linux-mmc@...r.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>,
Linux ARM <linux-arm-kernel@...ts.infradead.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@...ts.infradead.org>,
linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v1 1/2] dt-bindings: mmc: mtk-sd: add hs400 dly3 setting
On Fri, Aug 27, 2021 at 1:53 PM Wenbin Mei <wenbin.mei@...iatek.com> wrote:
> Add hs400 dly3 setting for mtk-sd yaml
>
> Signed-off-by: Wenbin Mei <wenbin.mei@...iatek.com>
(...)
> + mediatek,hs400-ds-dly3:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + HS400 DS dly3 delay setting.
> + minimum: 0
> + maximum: 31
Which unit is this? Clock cycles? Then please write that in the
binding description.
Yours,
Linus Walleij
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