linux-kernel - Re: [RESEND PATCH 2/2] arm64: dts: rockchip: add Coresight debug range for RK3399

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Date:   Wed, 8 Sep 2021 10:09:31 +0800
From:   Leo Yan <leo.yan@...aro.org>
To:     Brian Norris <briannorris@...omium.org>
Cc:     Heiko Stuebner <heiko@...ech.de>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>, linux-clk@...r.kernel.org,
        Chen-Yu Tsai <wenst@...omium.org>,
        Douglas Anderson <dianders@...omium.org>,
        linux-kernel@...r.kernel.org, linux-rockchip@...ts.infradead.org,
        linux-arm-kernel@...ts.infradead.org
Subject: Re: [RESEND PATCH 2/2] arm64: dts: rockchip: add Coresight debug
 range for RK3399

On Tue, Sep 07, 2021 at 09:46:37AM -0700, Brian Norris wrote:
> Per Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt.
> 
> This IP block can be used for sampling the PC of any given CPU, which is
> useful in certain panic scenarios where you can't get the CPU to stop
> cleanly (e.g., hard lockup).
> 
> Signed-off-by: Brian Norris <briannorris@...omium.org>

Looks good to me, FWIW:

Reviewed-by: Leo Yan <leo.yan@...aro.org>

> ---
> 
>  arch/arm64/boot/dts/rockchip/rk3399.dtsi | 48 ++++++++++++++++++++++++
>  1 file changed, 48 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> index 3871c7fd83b0..c8c62637b600 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -433,6 +433,54 @@ usbdrd_dwc3_1: usb@...00000 {
>  		};
>  	};
>  
> +	debug@...30000 {
> +		compatible = "arm,coresight-cpu-debug", "arm,primecell";
> +		reg = <0 0xfe430000 0 0x1000>;
> +		clocks = <&cru PCLK_COREDBG_L>;
> +		clock-names = "apb_pclk";
> +		cpu = <&cpu_l0>;
> +	};
> +
> +	debug@...32000 {
> +		compatible = "arm,coresight-cpu-debug", "arm,primecell";
> +		reg = <0 0xfe432000 0 0x1000>;
> +		clocks = <&cru PCLK_COREDBG_L>;
> +		clock-names = "apb_pclk";
> +		cpu = <&cpu_l1>;
> +	};
> +
> +	debug@...34000 {
> +		compatible = "arm,coresight-cpu-debug", "arm,primecell";
> +		reg = <0 0xfe434000 0 0x1000>;
> +		clocks = <&cru PCLK_COREDBG_L>;
> +		clock-names = "apb_pclk";
> +		cpu = <&cpu_l2>;
> +	};
> +
> +	debug@...36000 {
> +		compatible = "arm,coresight-cpu-debug", "arm,primecell";
> +		reg = <0 0xfe436000 0 0x1000>;
> +		clocks = <&cru PCLK_COREDBG_L>;
> +		clock-names = "apb_pclk";
> +		cpu = <&cpu_l3>;
> +	};
> +
> +	debug@...10000 {
> +		compatible = "arm,coresight-cpu-debug", "arm,primecell";
> +		reg = <0 0xfe610000 0 0x1000>;
> +		clocks = <&cru PCLK_COREDBG_B>;
> +		clock-names = "apb_pclk";
> +		cpu = <&cpu_b0>;
> +	};
> +
> +	debug@...10000 {
> +		compatible = "arm,coresight-cpu-debug", "arm,primecell";
> +		reg = <0 0xfe710000 0 0x1000>;
> +		clocks = <&cru PCLK_COREDBG_B>;
> +		clock-names = "apb_pclk";
> +		cpu = <&cpu_b1>;
> +	};
> +
>  	cdn_dp: dp@...00000 {
>  		compatible = "rockchip,rk3399-cdn-dp";
>  		reg = <0x0 0xfec00000 0x0 0x100000>;
> -- 
> 2.33.0.153.gba50c8fa24-goog
>