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Message-Id: <5589514eb2d20504725821807800b5bbccf36fe6.1631121222.git.greentime.hu@sifive.com>
Date: Thu, 9 Sep 2021 01:45:28 +0800
From: Greentime Hu <greentime.hu@...ive.com>
To: linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
aou@...s.berkeley.edu, palmer@...belt.com,
paul.walmsley@...ive.com, vincent.chen@...ive.com
Subject: [RFC PATCH v8 16/21] riscv: Initialize vector registers with proper vsetvli then it can work normally
It may cause an illegal instruction exception if it doesn't use vsetvli
before vmv.v.i v0, 0.
Co-developed-by: Han-Kuan Chen <hankuan.chen@...ive.com>
Signed-off-by: Han-Kuan Chen <hankuan.chen@...ive.com>
Signed-off-by: Greentime Hu <greentime.hu@...ive.com>
---
arch/riscv/kernel/head.S | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index cf331f138142..42eb3203fa77 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -442,6 +442,7 @@ ENTRY(reset_regs)
li t1, SR_VS
csrs CSR_STATUS, t1
+ vsetvli t1, x0, e8, m1
vmv.v.i v0, 0
vmv.v.i v1, 0
vmv.v.i v2, 0
--
2.31.1
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