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Message-Id: <20210910002143.175731-22-sashal@kernel.org>
Date: Thu, 9 Sep 2021 20:21:27 -0400
From: Sasha Levin <sashal@...nel.org>
To: linux-kernel@...r.kernel.org, stable@...r.kernel.org
Cc: Vladimir Oltean <vladimir.oltean@....com>,
Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
Sasha Levin <sashal@...nel.org>, linux-mips@...r.kernel.org,
devicetree@...r.kernel.org
Subject: [PATCH AUTOSEL 5.4 22/37] MIPS: mscc: ocelot: mark the phy-mode for internal PHY ports
From: Vladimir Oltean <vladimir.oltean@....com>
[ Upstream commit eba54cbb92d28b4f6dc1ed5f73f5187b09d82c08 ]
The ocelot driver was converted to phylink, and that expects a valid
phy_interface_t. Without a phy-mode, of_get_phy_mode returns
PHY_INTERFACE_MODE_NA, which is not ideal because phylink rejects that.
The ocelot driver was patched to treat PHY_INTERFACE_MODE_NA as
PHY_INTERFACE_MODE_INTERNAL to work with the broken DT blobs, but we
should fix the device trees and specify the phy-mode too.
Signed-off-by: Vladimir Oltean <vladimir.oltean@....com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@...ha.franken.de>
Signed-off-by: Sasha Levin <sashal@...nel.org>
---
arch/mips/boot/dts/mscc/ocelot_pcb120.dts | 4 ++++
arch/mips/boot/dts/mscc/ocelot_pcb123.dts | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
index 7da9ed2da248..8555fe3e9517 100644
--- a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
+++ b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
@@ -61,21 +61,25 @@ phy4: ethernet-phy@3 {
&port0 {
status = "okay";
phy-handle = <&phy0>;
+ phy-mode = "internal";
};
&port1 {
status = "okay";
phy-handle = <&phy1>;
+ phy-mode = "internal";
};
&port2 {
status = "okay";
phy-handle = <&phy2>;
+ phy-mode = "internal";
};
&port3 {
status = "okay";
phy-handle = <&phy3>;
+ phy-mode = "internal";
};
&port4 {
diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb123.dts b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
index 7d7e638791dd..0185045c7630 100644
--- a/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
+++ b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
@@ -49,19 +49,23 @@ &mdio0 {
&port0 {
status = "okay";
phy-handle = <&phy0>;
+ phy-mode = "internal";
};
&port1 {
status = "okay";
phy-handle = <&phy1>;
+ phy-mode = "internal";
};
&port2 {
status = "okay";
phy-handle = <&phy2>;
+ phy-mode = "internal";
};
&port3 {
status = "okay";
phy-handle = <&phy3>;
+ phy-mode = "internal";
};
--
2.30.2
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