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Message-Id: <1631238562-27081-1-git-send-email-shengjiu.wang@nxp.com>
Date: Fri, 10 Sep 2021 09:49:22 +0800
From: Shengjiu Wang <shengjiu.wang@....com>
To: timur@...nel.org, nicoleotsuka@...il.com, Xiubo.Lee@...il.com,
festevam@...il.com, broonie@...nel.org, perex@...ex.cz,
tiwai@...e.com, alsa-devel@...a-project.org
Cc: linuxppc-dev@...ts.ozlabs.org, linux-kernel@...r.kernel.org
Subject: [PATCH] ASoC: fsl_spdif: Add support for i.MX8ULP
On i.MX8ULP the spdif works with EDMA, so add compatible
string and soc specific data for i.MX8ULP.
Signed-off-by: Shengjiu Wang <shengjiu.wang@....com>
---
sound/soc/fsl/fsl_spdif.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c
index 8ffb1a6048d6..61ba08322f23 100644
--- a/sound/soc/fsl/fsl_spdif.c
+++ b/sound/soc/fsl/fsl_spdif.c
@@ -186,6 +186,16 @@ static struct fsl_spdif_soc_data fsl_spdif_imx8mm = {
.tx_formats = FSL_SPDIF_FORMATS_PLAYBACK,
};
+static struct fsl_spdif_soc_data fsl_spdif_imx8ulp = {
+ .imx = true,
+ .shared_root_clock = true,
+ .raw_capture_mode = false,
+ .interrupts = 1,
+ .tx_burst = 2, /* Applied for EDMA */
+ .rx_burst = 2, /* Applied for EDMA */
+ .tx_formats = SNDRV_PCM_FMTBIT_S24_LE, /* Applied for EDMA */
+};
+
/* Check if clk is a root clock that does not share clock source with others */
static inline bool fsl_spdif_can_set_clk_rate(struct fsl_spdif_priv *spdif, int clk)
{
@@ -1556,6 +1566,7 @@ static const struct of_device_id fsl_spdif_dt_ids[] = {
{ .compatible = "fsl,imx6sx-spdif", .data = &fsl_spdif_imx6sx, },
{ .compatible = "fsl,imx8qm-spdif", .data = &fsl_spdif_imx8qm, },
{ .compatible = "fsl,imx8mm-spdif", .data = &fsl_spdif_imx8mm, },
+ { .compatible = "fsl,imx8ulp-spdif", .data = &fsl_spdif_imx8ulp, },
{}
};
MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids);
--
2.17.1
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