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Message-ID: <20210910111529.12539-4-tanureal@opensource.cirrus.com>
Date: Fri, 10 Sep 2021 12:15:29 +0100
From: Lucas Tanure <tanureal@...nsource.cirrus.com>
To: Mark Brown <broonie@...nel.org>,
Sanjay R Mehta <sanju.mehta@....com>,
Nehal Bakulchandra Shah <Nehal-Bakulchandra.shah@....com>
CC: <linux-kernel@...r.kernel.org>, <linux-spi@...r.kernel.org>,
<patches@...nsource.cirrus.com>,
Lucas Tanure <tanureal@...nsource.cirrus.com>
Subject: [PATCH v2 4/4] spi: amd: Don't wait for a write-only transfer to finish
Return from a write-only transfer without waiting for
it to finish
But wait before a new transfer as the previous may
still happening and also wait before reading the data
from the FIFO
Signed-off-by: Lucas Tanure <tanureal@...nsource.cirrus.com>
---
Changes in v2:
Add wait before read data
New explanation
drivers/spi/spi-amd.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-amd.c b/drivers/spi/spi-amd.c
index 97838b57871c..4b3ac7aceaf6 100644
--- a/drivers/spi/spi-amd.c
+++ b/drivers/spi/spi-amd.c
@@ -115,11 +115,18 @@ static int amd_spi_busy_wait(struct amd_spi *amd_spi)
return 0;
}
-static void amd_spi_execute_opcode(struct amd_spi *amd_spi)
+static int amd_spi_execute_opcode(struct amd_spi *amd_spi)
{
+ int ret;
+
+ ret = amd_spi_busy_wait(amd_spi);
+ if (ret)
+ return ret;
+
/* Set ExecuteOpCode bit in the CTRL0 register */
amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD, AMD_SPI_EXEC_CMD);
- amd_spi_busy_wait(amd_spi);
+
+ return 0;
}
static int amd_spi_master_setup(struct spi_device *spi)
@@ -178,6 +185,7 @@ static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi,
amd_spi_clear_fifo_ptr(amd_spi);
/* Execute command */
amd_spi_execute_opcode(amd_spi);
+ amd_spi_busy_wait(amd_spi);
/* Read data from FIFO to receive buffer */
for (i = 0; i < rx_len; i++)
buf[i] = amd_spi_readreg8(amd_spi, AMD_SPI_FIFO_BASE + tx_len + i);
--
2.33.0
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