linux-kernel - [RFC PATCH V4 6/6] riscv: soc: Add Allwinner SoC kconfig option

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Message-Id: <20210911092139.79607-7-guoren@kernel.org>
Date:   Sat, 11 Sep 2021 17:21:39 +0800
From:   guoren@...nel.org
To:     anup.patel@....com, atish.patra@....com, palmerdabbelt@...gle.com,
        guoren@...nel.org, christoph.muellner@...ll.eu,
        philipp.tomsich@...ll.eu, hch@....de, liush@...winnertech.com,
        wefu@...hat.com, lazyparser@...il.com, drew@...gleboard.org
Cc:     linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
        taiten.peng@...onical.com, aniket.ponkshe@...onical.com,
        heinrich.schuchardt@...onical.com, gordan.markus@...onical.com,
        Guo Ren <guoren@...ux.alibaba.com>,
        Chen-Yu Tsai <wens@...e.org>, Maxime Ripard <maxime@...no.tech>
Subject: [RFC PATCH V4 6/6] riscv: soc: Add Allwinner SoC kconfig option

From: Liu Shaohua <liush@...winnertech.com>

Add Allwinner kconfig option which selects SoC specific and common
drivers that is required for this SoC.

Allwinner D1 uses custom PTE attributes to solve non-coherency SOC
interconnect issues for dma synchronization, so we set the default
value when SOC_SUNXI selected.

Signed-off-by: Liu Shaohua <liush@...winnertech.com>
Signed-off-by: Guo Ren <guoren@...ux.alibaba.com>
Signed-off-by: Wei Fu <wefu@...hat.com>
Cc: Anup Patel <anup.patel@....com>
Cc: Atish Patra <atish.patra@....com>
Cc: Christoph Hellwig <hch@....de>
Cc: Chen-Yu Tsai <wens@...e.org>
Cc: Drew Fustini <drew@...gleboard.org>
Cc: Maxime Ripard <maxime@...no.tech>
Cc: Palmer Dabbelt <palmerdabbelt@...gle.com>
Cc: Wei Wu <lazyparser@...il.com>
---
 arch/riscv/Kconfig.socs      | 15 +++++++++++++++
 arch/riscv/configs/defconfig |  1 +
 2 files changed, 16 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 30676ebb16eb..8721c000ef23 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -70,4 +70,19 @@ config SOC_CANAAN_K210_DTB_SOURCE
 
 endif
 
+config SOC_SUNXI
+	bool "Allwinner SoCs"
+	depends on MMU
+	select DWMAC_GENERIC
+	select ERRATA_THEAD
+	select RISCV_DMA_NONCOHERENT
+	select RISCV_ERRATA_ALTERNATIVE
+	select SERIAL_8250
+	select SERIAL_8250_CONSOLE
+	select SERIAL_8250_DW
+	select SIFIVE_PLIC
+	select STMMAC_ETH
+	help
+	  This enables support for Allwinner SoC platforms like the D1.
+
 endmenu
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index bc68231a8fb7..a50f250fbdd8 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -15,6 +15,7 @@ CONFIG_BLK_DEV_INITRD=y
 CONFIG_EXPERT=y
 CONFIG_BPF_SYSCALL=y
 CONFIG_SOC_SIFIVE=y
+CONFIG_SOC_SUNXI=y
 CONFIG_SOC_VIRT=y
 CONFIG_SOC_MICROCHIP_POLARFIRE=y
 CONFIG_SMP=y
-- 
2.25.1