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Message-Id: <20210913131117.962802327@linuxfoundation.org>
Date: Mon, 13 Sep 2021 15:13:10 +0200
From: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To: linux-kernel@...r.kernel.org
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
stable@...r.kernel.org, Marek Vasut <marex@...x.de>,
Daniel Abrecht <public@...ielabrecht.ch>,
Emil Velikov <emil.l.velikov@...il.com>,
Laurent Pinchart <laurent.pinchart@...asonboard.com>,
Lucas Stach <l.stach@...gutronix.de>,
Stefan Agner <stefan@...er.ch>,
Jagan Teki <jagan@...rulasolutions.com>,
Sam Ravnborg <sam@...nborg.org>,
Sasha Levin <sashal@...nel.org>
Subject: [PATCH 5.14 136/334] drm: mxsfb: Clear FIFO_CLEAR bit
From: Marek Vasut <marex@...x.de>
[ Upstream commit 5e23c98178eb1a2cdb7c4fee9a39baf8cabf282d ]
Make sure the FIFO_CLEAR bit is latched in when configuring the
controller, so that the FIFO is really cleared. And then clear
the FIFO_CLEAR bit, since it is not self-clearing.
Fixes: 45d59d704080 ("drm: Add new driver for MXSFB controller")
Signed-off-by: Marek Vasut <marex@...x.de>
Cc: Daniel Abrecht <public@...ielabrecht.ch>
Cc: Emil Velikov <emil.l.velikov@...il.com>
Cc: Laurent Pinchart <laurent.pinchart@...asonboard.com>
Cc: Lucas Stach <l.stach@...gutronix.de>
Cc: Stefan Agner <stefan@...er.ch>
Reviewed-by: Jagan Teki <jagan@...rulasolutions.com>
Tested-by: Jagan Teki <jagan@...rulasolutions.com> # i.Core MX8MM
Acked-by: Lucas Stach <l.stach@...gutronix.de>
Signed-off-by: Sam Ravnborg <sam@...nborg.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20210620224946.189524-1-marex@denx.de
Signed-off-by: Sasha Levin <sashal@...nel.org>
---
drivers/gpu/drm/mxsfb/mxsfb_kms.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_kms.c b/drivers/gpu/drm/mxsfb/mxsfb_kms.c
index 5bcc06c1ac0b..54f905ac75c0 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_kms.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_kms.c
@@ -243,6 +243,9 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)
/* Clear the FIFOs */
writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_SET);
+ readl(mxsfb->base + LCDC_CTRL1);
+ writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_CLR);
+ readl(mxsfb->base + LCDC_CTRL1);
if (mxsfb->devdata->has_overlay)
writel(0, mxsfb->base + LCDC_AS_CTRL);
--
2.30.2
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