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Message-Id: <1631554694-9599-15-git-send-email-abel.vesa@nxp.com>
Date: Mon, 13 Sep 2021 20:38:09 +0300
From: Abel Vesa <abel.vesa@....com>
To: Rob Herring <robh@...nel.org>, Dong Aisheng <aisheng.dong@....com>,
Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
"catalin.marinas@....com" <catalin.marinas@....com>,
Will Deacon <will.deacon@....com>,
MyungJoo Ham <myungjoo.ham@...sung.com>,
Kyungmin Park <kyungmin.park@...sung.com>,
Chanwoo Choi <cw00.choi@...sung.com>,
Georgi Djakov <djakov@...nel.org>,
Adrian Hunter <adrian.hunter@...el.com>,
Ulf Hansson <ulf.hansson@...aro.org>,
Ahmad Fatoum <a.fatoum@...gutronix.de>
Cc: Pengutronix Kernel Team <kernel@...gutronix.de>,
linux-serial@...r.kernel.org, NXP Linux Team <linux-imx@....com>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
devicetree@...r.kernel.org, linux-pm@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, Abel Vesa <abel.vesa@....com>
Subject: [RFC 14/19] arm64: dts: imx8mq: Add all pl301 nodes
Add all the pl301s found on i.MX8MQ, according to the bus diagram.
Each pl301 has its own clock, icc id and opp table. They are probed
by the imx-bus driver.
Signed-off-by: Abel Vesa <abel.vesa@....com>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 202 ++++++++++++++++++++++
1 file changed, 202 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index ab528665a217..a05bccbb1342 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1566,5 +1566,207 @@ ddr-pmu@...00000 {
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ pl301_main: pl301@0 {
+ compatible = "fsl,imx8m-nic";
+ clocks = <&clk IMX8MQ_CLK_MAIN_AXI>;
+ operating-points-v2 = <&pl301_main_opp_table>;
+ #interconnect-cells = <0>;
+ fsl,icc-id = <IMX8MQ_ICN_MAIN>;
+
+ pl301_main_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25M {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+ opp-133M {
+ opp-hz = /bits/ 64 <133333333>;
+ };
+ opp-333M {
+ opp-hz = /bits/ 64 <333333333>;
+ };
+ };
+ };
+
+ pl301_enet: pl301@1 {
+ compatible = "fsl,imx8m-nic";
+ clocks = <&clk IMX8MQ_CLK_ENET_AXI>;
+ operating-points-v2 = <&pl301_enet_opp_table>;
+ #interconnect-cells = <0>;
+ fsl,icc-id = <IMX8MQ_ICN_ENET>;
+
+ pl301_enet_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25M {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+ opp-266M {
+ opp-hz = /bits/ 64 <266666666>;
+ };
+ };
+ };
+
+ pl301_gpu: pl301@2 {
+ compatible = "fsl,imx8m-nic";
+ clocks = <&clk IMX8MQ_CLK_GPU_AXI>;
+ operating-points-v2 = <&pl301_gpu_opp_table>;
+ #interconnect-cells = <0>;
+ fsl,icc-id = <IMX8MQ_ICN_GPU>;
+
+ pl301_gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25M {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+ opp-800M {
+ opp-hz = /bits/ 64 <800000000>;
+ };
+ };
+ };
+
+ pl301_dc: pl301@3 {
+ compatible = "fsl,imx8m-nic";
+ clocks = <&clk IMX8MQ_CLK_DISP_AXI>;
+ operating-points-v2 = <&pl301_dc_opp_table>;
+ #interconnect-cells = <0>;
+ fsl,icc-id = <IMX8MQ_ICN_DCSS>;
+
+ pl301_dc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25M {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+ opp-800M {
+ opp-hz = /bits/ 64 <800000000>;
+ };
+ };
+ };
+
+ /* PL301_DISPLAY (IPs other than DCSS, inside SUPERMIX) */
+ pl301_display: pl301@4 {
+ compatible = "fsl,imx8m-nic";
+ /* FIXME: don't know which clock yet */
+ clocks = <&clk IMX8MQ_CLK_DUMMY>;
+ operating-points-v2 = <&pl301_display_opp_table>;
+ #interconnect-cells = <0>;
+ fsl,icc-id = <IMX8MQ_ICN_DISPLAY>;
+
+ pl301_display_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25M {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+ opp-333M {
+ opp-hz = /bits/ 64 <333333333>;
+ };
+ };
+ };
+
+ pl301_audio: pl301@5 {
+ compatible = "fsl,imx8m-nic";
+ clocks = <&clk IMX8MQ_CLK_AUDIO_AHB>;
+ operating-points-v2 = <&pl301_audio_opp_table>;
+ #interconnect-cells = <0>;
+ fsl,icc-id = <IMX8MQ_ICN_AUDIO>;
+
+ pl301_audio_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25M {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+ opp-500M {
+ opp-hz = /bits/ 64 <500000000>;
+ };
+ };
+ };
+
+ pl301_video: pl301@6 {
+ compatible = "fsl,imx8m-nic";
+ clocks = <&clk IMX8MQ_CLK_VPU_BUS>;
+ operating-points-v2 = <&pl301_video_opp_table>;
+ #interconnect-cells = <0>;
+ fsl,icc-id = <IMX8MQ_ICN_VIDEO>;
+
+ pl301_video_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25M {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+ opp-500M {
+ opp-hz = /bits/ 64 <500000000>;
+ };
+ };
+ };
+
+ pl301_usb: pl301@7 {
+ compatible = "fsl,imx8m-nic";
+ clocks = <&clk IMX8MQ_CLK_USB_BUS>;
+ operating-points-v2 = <&pl301_usb_opp_table>;
+ #interconnect-cells = <0>;
+ fsl,icc-id = <IMX8MQ_ICN_USB>;
+
+ pl301_usb_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25M {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+ opp-128M {
+ opp-hz = /bits/ 64 <128000000>;
+ };
+ opp-500M {
+ opp-hz = /bits/ 64 <500000000>;
+ };
+ };
+ };
+
+ pl301_wakeup: pl301@8 {
+ compatible = "fsl,imx8m-nic";
+ /* FIXME: don't know which clock yet */
+ clocks = <&clk IMX8MQ_CLK_DUMMY>;
+ operating-points-v2 = <&pl301_wakeup_opp_table>;
+ #interconnect-cells = <0>;
+ fsl,icc-id = <IMX8MQ_ICN_WAKEUP>;
+
+ pl301_wakeup_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25M {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+ opp-133M {
+ opp-hz = /bits/ 64 <133333333>;
+ };
+ };
+ };
+
+ pl301_per_m: pl301@9 {
+ compatible = "fsl,imx8m-nic";
+ clocks = <&clk IMX8MQ_CLK_NAND_USDHC_BUS>;
+ operating-points-v2 = <&pl301_per_m_opp_table>;
+ #interconnect-cells = <0>;
+ fsl,icc-id = <IMX8MQ_ICN_PER_M>;
+
+ pl301_per_m_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25M {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+ opp-133M {
+ opp-hz = /bits/ 64 <133333333>;
+ };
+ opp-266M {
+ opp-hz = /bits/ 64 <266666666>;
+ };
+ };
+ };
};
};
--
2.31.1
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