linux-kernel - [RFC 16/19] arm64: dts: imx8mq: Add interconnect properties to icc consumer nodes

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Message-Id: <1631554694-9599-17-git-send-email-abel.vesa@nxp.com>
Date:   Mon, 13 Sep 2021 20:38:11 +0300
From:   Abel Vesa <abel.vesa@....com>
To:     Rob Herring <robh@...nel.org>, Dong Aisheng <aisheng.dong@....com>,
        Shawn Guo <shawnguo@...nel.org>,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Fabio Estevam <festevam@...il.com>,
        "catalin.marinas@....com" <catalin.marinas@....com>,
        Will Deacon <will.deacon@....com>,
        MyungJoo Ham <myungjoo.ham@...sung.com>,
        Kyungmin Park <kyungmin.park@...sung.com>,
        Chanwoo Choi <cw00.choi@...sung.com>,
        Georgi Djakov <djakov@...nel.org>,
        Adrian Hunter <adrian.hunter@...el.com>,
        Ulf Hansson <ulf.hansson@...aro.org>,
        Ahmad Fatoum <a.fatoum@...gutronix.de>
Cc:     Pengutronix Kernel Team <kernel@...gutronix.de>,
        linux-serial@...r.kernel.org, NXP Linux Team <linux-imx@....com>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        devicetree@...r.kernel.org, linux-pm@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, Abel Vesa <abel.vesa@....com>
Subject: [RFC 16/19] arm64: dts: imx8mq: Add interconnect properties to icc consumer nodes

We add all the properties necessary to control the interconnect
based on the required rates all the way from consumers to the dram.
The fsl,icc-rate specifies the minimum required rate the consumer needs
in order to operate.
For now, only the fec, usdhc1 and usdhc2 are added as consumers.

Signed-off-by: Abel Vesa <abel.vesa@....com>
---
 arch/arm64/boot/dts/freescale/imx8mq.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 5a73ebda6bb3..0489f7416993 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1215,6 +1215,9 @@ usdhc1: mmc@...40000 {
 				             "fsl,imx7d-usdhc";
 				reg = <0x30b40000 0x10000>;
 				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&icc IMX8MQ_ICM_USDHC1 &icc IMX8MQ_ICS_DRAM>;
+				interconnect-names = "path";
+				fsl,icc-rate = <266666>;
 				clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
 				         <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
 				         <&clk IMX8MQ_CLK_USDHC1_ROOT>;
@@ -1230,6 +1233,9 @@ usdhc2: mmc@...50000 {
 				             "fsl,imx7d-usdhc";
 				reg = <0x30b50000 0x10000>;
 				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&icc IMX8MQ_ICM_USDHC2 &icc IMX8MQ_ICS_DRAM>;
+				interconnect-names = "path";
+				fsl,icc-rate = <266666>;
 				clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
 				         <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
 				         <&clk IMX8MQ_CLK_USDHC2_ROOT>;
@@ -1272,6 +1278,9 @@ fec1: ethernet@...e0000 {
 				             <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&icc IMX8MQ_ICM_ENET &icc IMX8MQ_ICS_DRAM>;
+				interconnect-names = "path";
+				fsl,icc-rate = <800000>;
 				clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
 				         <&clk IMX8MQ_CLK_ENET1_ROOT>,
 				         <&clk IMX8MQ_CLK_ENET_TIMER>,
-- 
2.31.1