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Message-ID: <20210914090338.5945-6-hsin-hsiung.wang@mediatek.com>
Date: Tue, 14 Sep 2021 17:03:38 +0800
From: Hsin-Hsiung Wang <hsin-hsiung.wang@...iatek.com>
To: Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>
CC: Hsin-Hsiung Wang <hsin-hsiung.wang@...iatek.com>,
<linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>,
<srv_heupstream@...iatek.com>,
<Project_Global_Chrome_Upstream_Group@...iatek.com>
Subject: [PATCH v12 5/5] arm64: dts: mt8192: add spmi node
Add spmi node to SOC MT8192.
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@...iatek.com>
---
changes since v11:
- No change.
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 9810f1d441da..1237e3624e44 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -316,6 +316,23 @@
clock-names = "clk13m";
};
+ spmi: spmi@...27000 {
+ compatible = "mediatek,mt6873-spmi";
+ reg = <0 0x10027000 0 0x000e00>,
+ <0 0x10029000 0 0x000100>;
+ reg-names = "pmif", "spmimst";
+ clocks = <&infracfg CLK_INFRA_PMIC_AP>,
+ <&infracfg CLK_INFRA_PMIC_TMR>,
+ <&topckgen CLK_TOP_SPMI_MST_SEL>;
+ clock-names = "pmif_sys_ck",
+ "pmif_tmr_ck",
+ "spmimst_clk_mux";
+ assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
+
scp_adsp: clock-controller@...20000 {
compatible = "mediatek,mt8192-scp_adsp";
reg = <0 0x10720000 0 0x1000>;
--
2.18.0
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