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Message-Id: <06263cbc-70f1-4484-86f3-3735137b3a8f@www.fastmail.com>
Date: Tue, 14 Sep 2021 15:56:55 +0200
From: "Sven Peter" <sven@...npeter.dev>
To: "Marc Zyngier" <maz@...nel.org>
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-pci@...r.kernel.org, "Bjorn Helgaas" <bhelgaas@...gle.com>,
"Rob Herring" <robh+dt@...nel.org>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@....com>,
Krzysztof WilczyĆski <kw@...ux.com>,
"Alyssa Rosenzweig" <alyssa@...enzweig.io>,
"Stan Skowronek" <stan@...ellium.com>,
"Mark Kettenis" <kettenis@...nbsd.org>,
"Hector Martin" <marcan@...can.st>,
"Robin Murphy" <Robin.Murphy@....com>, kernel-team@...roid.com
Subject: Re: [PATCH v3 10/10] PCI: apple: Configure RID to SID mapper on device addition
On Tue, Sep 14, 2021, at 11:35, Marc Zyngier wrote:
> On Mon, 13 Sep 2021 21:45:13 +0100,
> "Sven Peter" <sven@...npeter.dev> wrote:
> >
> >
> >
> > On Mon, Sep 13, 2021, at 20:25, Marc Zyngier wrote:
> > > The Apple PCIe controller doesn't directly feed the endpoint's
> > > Requester ID to the IOMMU (DART), but instead maps RIDs onto
> > > Stream IDs (SIDs). The DART and the PCIe controller must thus
> > > agree on the SIDs that are used for translation (by using
> > > the 'iommu-map' property).
> > >
> > > For this purpose, parse the 'iommu-map' property each time a
> > > device gets added, and use the resulting translation to configure
> > > the PCIe RID-to-SID mapper. Similarily, remove the translation
> > > if/when the device gets removed.
> > >
> > > This is all driven from a bus notifier which gets registered at
> > > probe time. Hopefully this is the only PCI controller driver
> > > in the whole system.
> > >
> > > Signed-off-by: Marc Zyngier <maz@...nel.org>
> > > ---
> > > drivers/pci/controller/pcie-apple.c | 158 +++++++++++++++++++++++++++-
> > > 1 file changed, 156 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/pci/controller/pcie-apple.c
> > > b/drivers/pci/controller/pcie-apple.c
> > > index 76344223245d..68d71eabe708 100644
> > > --- a/drivers/pci/controller/pcie-apple.c
> > > +++ b/drivers/pci/controller/pcie-apple.c
> > > @@ -23,8 +23,10 @@
> > > #include <linux/iopoll.h>
> > > #include <linux/irqchip/chained_irq.h>
> > > #include <linux/irqdomain.h>
> > > +#include <linux/list.h>
> > > #include <linux/module.h>
> > > #include <linux/msi.h>
> > > +#include <linux/notifier.h>
> > > #include <linux/of_irq.h>
> > > #include <linux/pci-ecam.h>
> > >
> > > @@ -116,6 +118,8 @@
> > > #define PORT_TUNSTAT_PERST_ACK_PEND BIT(1)
> > > #define PORT_PREFMEM_ENABLE 0x00994
> > >
> > > +#define MAX_RID2SID 64
> >
> > Do these actually have 64 slots? I thought that was only for
> > the Thunderbolt controllers and that these only had 16.
>
> You are indeed right, and I blindly used the limit used in the
> Correlium driver. Using entries from 16 onward result in a non booting
> system. The registers do not fault though, and simply ignore writes. I
> came up with an simple fix for this, see below.
Looks good to me and at least I prefer that to an additional property
in the device tree.
Reviewed-by: Sven Peter <sven@...npeter.dev>
Thanks,
Sven
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