linux-kernel - [PATCH 5.14 033/432] soc: mediatek: mmsys: Fix missing UFOE component in mt8173 table routing

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Message-Id: <20210916155811.942436912@linuxfoundation.org>
Date:   Thu, 16 Sep 2021 17:56:22 +0200
From:   Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To:     linux-kernel@...r.kernel.org
Cc:     Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        stable@...r.kernel.org,
        Enric Balletbo i Serra <enric.balletbo@...labora.com>,
        Eizan Miyamoto <eizan@...omium.org>,
        Matthias Brugger <matthias.bgg@...il.com>
Subject: [PATCH 5.14 033/432] soc: mediatek: mmsys: Fix missing UFOE component in mt8173 table routing

From: Enric Balletbo i Serra <enric.balletbo@...labora.com>

commit 25423731956b3d72bc35d336227c88ada49148e8 upstream.

The UFOE (data compression engine) component needs to be enabled to have
the imgtec gpu driver working. If we don't enable it we see a black screen.
Looks like when we switched to use and array for setting the routing
registers in commit 440147639ac7 ("soc: mediatek: mmsys: Use an array for
setting the routing registers") we missed to add this component in the new
routing table, it was present before that commit, so fix it by adding
this component in the mt8173 routing table.

Fixes: 440147639ac7 ("soc: mediatek: mmsys: Use an array for setting the routing registers")
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@...labora.com>
Tested-by: Eizan Miyamoto <eizan@...omium.org>
Cc: <stable@...r.kernel.org>
Link: https://lore.kernel.org/r/20210625062448.3462177-1-enric.balletbo@collabora.com
[mb: taking into account mask value]
Signed-off-by: Matthias Brugger <matthias.bgg@...il.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
---
 drivers/soc/mediatek/mtk-mmsys.h |    4 ++++
 1 file changed, 4 insertions(+)

--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -262,6 +262,10 @@ static const struct mtk_mmsys_routes mms
 		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,
 		DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,
 		DSI3_SEL_IN_RDMA2
+	}, {
+		DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0,
+		DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, UFOE_MOUT_EN_DSI0,
+		UFOE_MOUT_EN_DSI0
 	}
 };