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Message-ID: <20210916130855.4054926-2-chenhuang5@huawei.com>
Date: Thu, 16 Sep 2021 13:08:54 +0000
From: Chen Huang <chenhuang5@...wei.com>
To: Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>
CC: Chen Huang <chenhuang5@...wei.com>,
Kefeng Wang <wangkefeng.wang@...wei.com>,
Darius Rad <darius@...espec.com>,
Jisheng Zhang <jszhang3@...l.ustc.edu.cn>,
<linux-riscv@...ts.infradead.org>, <linux-kernel@...r.kernel.org>
Subject: [PATCH v2 1/2] riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS
This patch selects HAVE_EFFICIENT_UNALIGNED_ACCESS. But the feature
maybe not be implemented on some CPUs, or with inefficent
implementation. So add a config CPU_HAS_NO_UNALIGNED, if the CPU
don't want it, please select it.
Signed-off-by: Chen Huang <chenhuang5@...wei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@...wei.com>
---
arch/riscv/Kconfig | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index aac669a6c3d8..cd0be39d4c08 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -81,6 +81,7 @@ config RISCV
select HAVE_DEBUG_KMEMLEAK
select HAVE_DMA_CONTIGUOUS if MMU
select HAVE_EBPF_JIT if MMU
+ select HAVE_EFFICIENT_UNALIGNED_ACCESS if !CPU_HAS_NO_UNALIGNED && MMU
select HAVE_FUNCTION_ERROR_INJECTION
select HAVE_FUTEX_CMPXCHG if FUTEX
select HAVE_GCC_PLUGINS
@@ -382,6 +383,9 @@ config FPU
If you don't know what to do here, say Y.
+config CPU_HAS_NO_UNALIGNED
+ bool
+
endmenu
menu "Kernel features"
--
2.25.1
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