Date:   Fri, 17 Sep 2021 09:00:47 -0700
From:   Doug Anderson <dianders@...omium.org>
To:     Rajendra Nayak <rnayak@...eaurora.org>
Cc:     Bjorn Andersson <bjorn.andersson@...aro.org>,
        Andy Gross <agross@...nel.org>,
        LinusW <linus.walleij@...aro.org>,
        linux-arm-msm <linux-arm-msm@...r.kernel.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        LKML <linux-kernel@...r.kernel.org>,
        Prasad Sodagudi <psodagud@...eaurora.org>
Subject: Re: [PATCH] pinctrl: qcom: Add egpio feature support

Hi,

On Thu, Sep 16, 2021 at 11:38 PM Rajendra Nayak <rnayak@...eaurora.org> wrote:
>
> From: Prasad Sodagudi <psodagud@...eaurora.org>
>
> egpio is a scheme which allows special power Island Domain IOs
> (LPASS,SSC) to be reused as regular chip GPIOs by muxing regular
> TLMM functions with Island Domain functions.
> With this scheme, an IO can be controlled both by the cpu running
> linux and the Island processor. This provides great flexibility to
> re-purpose the Island IOs for regular TLMM usecases.
>
> 2 new bits are added to ctl_reg, egpio_present is a read only bit
> which shows if egpio feature is available or not on a given gpio.
> egpio_enable is the read/write bit and only effective if egpio_present
> is 1. Once its set, the Island IO is controlled from Chip TLMM.
> egpio_enable when set to 0 means the GPIO is used as Island Domain IO.
>
> The support exists on most recent qcom SoCs, and we add support
> for sm8150/sm8250/sm8350 and sc7280 as part of this patch.
>
> Signed-off-by: Prasad Sodagudi <psodagud@...eaurora.org>
> [rnayak: rewrite commit log, minor rebase]
> Signed-off-by: Rajendra Nayak <rnayak@...eaurora.org>
> ---
>  drivers/pinctrl/qcom/pinctrl-msm.c    | 4 ++++
>  drivers/pinctrl/qcom/pinctrl-msm.h    | 2 ++
>  drivers/pinctrl/qcom/pinctrl-sc7280.c | 2 ++
>  drivers/pinctrl/qcom/pinctrl-sm8150.c | 2 ++
>  drivers/pinctrl/qcom/pinctrl-sm8250.c | 2 ++
>  drivers/pinctrl/qcom/pinctrl-sm8350.c | 2 ++
>  6 files changed, 14 insertions(+)
>
> diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
> index 8476a8a..f4a2343 100644
> --- a/drivers/pinctrl/qcom/pinctrl-msm.c
> +++ b/drivers/pinctrl/qcom/pinctrl-msm.c
> @@ -220,6 +220,10 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
>         val = msm_readl_ctl(pctrl, g);
>         val &= ~mask;
>         val |= i << g->mux_bit;
> +       /* Check if egpio present and enable that feature */

nit: blank line above the comment?

> +       if (val & BIT(g->egpio_present))
> +               val |= BIT(g->egpio_enable);

Thinking about this on systems that don't support egpio,
g->egpio_present will be 0, right? BIT(0) = 1, so I guess this is
equivalent to the code below on non-eGPIO systems:

  if (val & 1)
    val |= 1;

I guess that's not the end of the world (it's a noop) and I can't
think of anything better. In theory you could add a boolean
"egpio_used" or you could just assume egpio is used if "egpio_present"
!= "egpio_enable", but all of those seem like a waste. Maybe just
change the comment to something like:

/*
 * Check if egpio present and enable that feature. For SoCs that
 * don't support egpio `egpio_present` will equal `egpio_enable` (they
 * will both be zero) and the statement below will be a no-op.
 */

Another question I have is: don't we need a way to turn off
egpio_enable? Maybe this should be something like this:

if (val & BIT(g->egpio_present)) {
  if (i == gpio_func)
    val |= BIT(g->egpio_enable);
  else
    val &= ~BIT(g->egpio_enable);
}

...oh, but then you probably _do_ need to check if "egpio_present" !=
"egpio_enable" since the clearing of the bit won't be a no-op on
non-egpio SoCs.

-Doug

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