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Date: Thu, 16 Sep 2021 23:24:10 -0700
From: Stephen Boyd <swboyd@...omium.org>
To: Rakesh Pillai <pillair@...eaurora.org>, agross@...nel.org,
bjorn.andersson@...aro.org, mathieu.poirier@...aro.org,
ohad@...ery.com, p.zabel@...gutronix.de, robh+dt@...nel.org
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, sibis@...eaurora.org,
mpubbise@...eaurora.org, kuabhs@...omium.org,
Rakesh Pillai <pillair@....qualcomm.com>
Subject: Re: [PATCH v3 1/3] dt-bindings: remoteproc: qcom: adsp: Convert
binding to YAML
Quoting Rakesh Pillai (2021-09-16 09:55:51)
> diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.yaml
> new file mode 100644
> index 0000000..051da43
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.yaml
> @@ -0,0 +1,267 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/remoteproc/qcom,hexagon-v56.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Hexagon v56 Peripheral Image Loader
> +
> +maintainers:
> + - Bjorn Andersson <bjorn.andersson@...aro.org>
> +
> +description:
> + This document defines the binding for a component that loads and boots firmware
> + on the Qualcomm Technology Inc. Hexagon v56 core.
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,qcs404-cdsp-pil
> + - qcom,sdm845-adsp-pil
> +
> + reg:
> + maxItems: 1
> + description:
> + The base address and size of the qdsp6ss register
> +
> + interrupts-extended:
> + minItems: 5
> + items:
> + - description: Watchdog interrupt
> + - description: Fatal interrupt
> + - description: Ready interrupt
> + - description: Handover interrupt
> + - description: Stop acknowledge interrupt
> +
> + interrupt-names:
> + minItems: 5
> + items:
> + - const: wdog
> + - const: fatal
> + - const: ready
> + - const: handover
> + - const: stop-ack
> +
> + clocks:
> + minItems: 7
> + maxItems: 8
> + description:
> + List of phandles and clock specifier pairs for the Hexagon,
> + per clock-names below.
> +
> + clock-names:
> + minItems: 7
> + maxItems: 8
> +
> + power-domains:
> + minItems: 1
> + items:
> + - description: CX power domain
> +
> + resets:
> + minItems: 1
> + maxItems: 2
> + description:
> + reference to the list of resets for the Hexagon.
> +
> + reset-names:
> + minItems: 1
> + maxItems: 2
> +
> + memory-region:
> + maxItems: 1
> + description: Reference to the reserved-memory for the Hexagon core
> +
> + qcom,halt-regs:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description:
> + Phandle reference to a syscon representing TCSR followed by the
> + three offsets within syscon for q6, modem and nc halt registers.
> +
> + qcom,smem-states:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: States used by the AP to signal the Hexagon core
> + items:
> + - description: Stop the modem
> +
> + qcom,smem-state-names:
> + $ref: /schemas/types.yaml#/definitions/string-array
> + description: The names of the state bits used for SMP2P output
> + items:
> + - const: stop
> +
> + glink-edge:
> + type: object
> + description:
> + Qualcomm G-Link subnode which represents communication edge, channels
> + and devices related to the ADSP.
> +
> +required:
> + - compatible
> + - reg
> + - interrupts-extended
> + - interrupt-names
> + - clocks
> + - clock-names
> + - power-domains
> + - qcom,halt-regs
> + - memory-region
> + - qcom,smem-states
> + - qcom,smem-state-names
Is there some way to make sure that 'resets' and 'reset-names' is
present when the compatible that defines them is used and not required
otherwise?
> +
> +additionalProperties: false
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sdm845-adsp-pil
> + then:
> + properties:
> + clocks:
> + items:
> + - description: XO clock
> + - description: SWAY clock
> + - description: LPASS AHBS AON clock
> + - description: LPASS AHBM AON clock
> + - description: QDSP6SS XO clock
> + - description: QDSP6SS SLEEP clock
> + - description: QDSP6SS CORE clock
> + clock-names:
> + items:
> + - const: xo
> + - const: sway_cbcr
> + - const: lpass_ahbs_aon_cbcr
> + - const: lpass_ahbm_aon_cbcr
> + - const: qdsp6ss_xo
> + - const: qdsp6ss_sleep
> + - const: qdsp6ss_core
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,qcs404-cdsp-pil
> + then:
> + properties:
> + clocks:
> + items:
> + - description: XO clock
> + - description: SWAY clock
> + - description: TBU clock
> + - description: BIMC clock
> + - description: AHB AON clock
> + - description: Q6SS SLAVE clock
> + - description: Q6SS MASTER clock
> + - description: Q6 AXIM clock
> + clock-names:
> + items:
> + - const: xo
> + - const: sway
> + - const: tbu
> + - const: bimc
> + - const: ahb_aon
> + - const: q6ss_slave
> + - const: q6ss_master
> + - const: q6_axim
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sc7280-wpss-pil
This should be documented above in the compatible list?
> + then:
> + properties:
> + clocks:
> + items:
> + - description: GCC WPSS AHB BDG Master clock
> + - description: GCC WPSS AHB clock
> + - description: GCC WPSS RSCP clock
> + clock-names:
> + items:
> + - const: gcc_wpss_ahb_bdg_mst_clk
> + - const: gcc_wpss_ahb_clk
> + - const: gcc_wpss_rscp_clk
Is the 'gcc_wpss' prefix important? It would be shorter if it wasn't
there.
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sdm845-adsp-pil
> + then:
> + properties:
> + resets:
> + items:
> + - description: PDC SYNC
> + - description: CC LPASS
> + reset-names:
> + items:
> + - const: pdc_sync
> + - const: cc_lpass
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,qcs404-cdsp-pil
> + then:
> + properties:
> + resets:
> + items:
> + - description: CDSP restart
> + reset-names:
> + items:
> + - const: restart
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/qcom,rpmh.h>
> + #include <dt-bindings/clock/qcom,gcc-sdm845.h>
> + #include <dt-bindings/clock/qcom,lpass-sdm845.h>
> + #include <dt-bindings/power/qcom-rpmpd.h>
> + #include <dt-bindings/reset/qcom,sdm845-pdc.h>
> + #include <dt-bindings/reset/qcom,sdm845-aoss.h>
> + remoteproc@...00000 {
> + compatible = "qcom,sdm845-adsp-pil";
> + reg = <0x17300000 0x40c>;
> +
> + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
> + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "wdog", "fatal", "ready",
> + "handover", "stop-ack";
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_LPASS_SWAY_CLK>,
> + <&lpasscc LPASS_Q6SS_AHBS_AON_CLK>,
> + <&lpasscc LPASS_Q6SS_AHBM_AON_CLK>,
> + <&lpasscc LPASS_QDSP6SS_XO_CLK>,
> + <&lpasscc LPASS_QDSP6SS_SLEEP_CLK>,
> + <&lpasscc LPASS_QDSP6SS_CORE_CLK>;
> + clock-names = "xo", "sway_cbcr",
> + "lpass_ahbs_aon_cbcr",
> + "lpass_ahbm_aon_cbcr", "qdsp6ss_xo",
> + "qdsp6ss_sleep", "qdsp6ss_core";
> +
> + power-domains = <&rpmhpd SDM845_CX>;
> +
> + resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>,
> + <&aoss_reset AOSS_CC_LPASS_RESTART>;
> + reset-names = "pdc_sync", "cc_lpass";
> +
> + qcom,halt-regs = <&tcsr_mutex_regs 0x22000>;
> +
> + memory-region = <&pil_adsp_mem>;
> +
> + qcom,smem-states = <&adsp_smp2p_out 0>;
> + qcom,smem-state-names = "stop";
> + };
Should there be two more examples for the other compatible strings here?
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