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Message-ID: <87o88rbmc7.wl-maz@kernel.org>
Date: Fri, 17 Sep 2021 10:08:56 +0100
From: Marc Zyngier <maz@...nel.org>
To: Alyssa Rosenzweig <alyssa@...enzweig.io>
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-pci@...r.kernel.org, Bjorn Helgaas <bhelgaas@...gle.com>,
Rob Herring <robh+dt@...nel.org>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Krzysztof WilczyĆski <kw@...ux.com>,
Stan Skowronek <stan@...ellium.com>,
Mark Kettenis <kettenis@...nbsd.org>,
Sven Peter <sven@...npeter.dev>,
Hector Martin <marcan@...can.st>,
Robin Murphy <Robin.Murphy@....com>, kernel-team@...roid.com
Subject: Re: [PATCH v3 08/10] PCI: apple: Implement MSI support
On Mon, 13 Sep 2021 21:43:23 +0100,
Alyssa Rosenzweig <alyssa@...enzweig.io> wrote:
>
> > +static void apple_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
> > +{
> > + BUILD_BUG_ON(upper_32_bits(DOORBELL_ADDR));
> > +
> > + msg->address_hi = upper_32_bits(DOORBELL_ADDR);
> > + msg->address_lo = lower_32_bits(DOORBELL_ADDR);
> > + msg->data = data->hwirq;
> > +}
> ...
> > @@ -269,6 +378,14 @@ static int apple_pcie_port_setup_irq(struct apple_pcie_port *port)
> >
> > irq_set_chained_handler_and_data(irq, apple_port_irq_handler, port);
> >
> > + /* Configure MSI base address */
> > + writel_relaxed(lower_32_bits(DOORBELL_ADDR), port->base + PORT_MSIADDR);
> > +
> > + /* Enable MSIs, shared between all ports */
> > + writel_relaxed(0, port->base + PORT_MSIBASE);
> > + writel_relaxed((ilog2(port->pcie->nvecs) << PORT_MSICFG_L2MSINUM_SHIFT) |
> > + PORT_MSICFG_EN, port->base + PORT_MSICFG);
> > +
> > return 0;
> > }
>
> I think the BUILD_BUG_ON makes more sense next to configuring the base
> address (which only has a 32-bit register, the BUILD_BUG_ON justifies
> using writel and not writeq), rather than configuring the message (which
> specifies the full 64-bits).
Indeed, this makes a bit more sense. Thanks for pointing this out.
M.
--
Without deviation from the norm, progress is not possible.
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