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Message-ID: <20210917120642.8993-15-claudiu.beznea@microchip.com>
Date: Fri, 17 Sep 2021 15:06:39 +0300
From: Claudiu Beznea <claudiu.beznea@...rochip.com>
To: <mturquette@...libre.com>, <sboyd@...nel.org>,
<nicolas.ferre@...rochip.com>, <alexandre.belloni@...tlin.com>,
<ludovic.desroches@...rochip.com>
CC: <linux-clk@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>,
Claudiu Beznea <claudiu.beznea@...rochip.com>
Subject: [PATCH v3 14/17] clk: at91: sama7g5: set low limit for mck0 at 32KHz
MCK0 could go as low as 32KHz. Set this limit.
Signed-off-by: Claudiu Beznea <claudiu.beznea@...rochip.com>
---
drivers/clk/at91/sama7g5.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index aaa5769a8df1..19cbe3db7f8a 100644
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -848,7 +848,7 @@ static const struct {
/* MCK0 characteristics. */
static const struct clk_master_characteristics mck0_characteristics = {
- .output = { .min = 50000000, .max = 200000000 },
+ .output = { .min = 32768, .max = 200000000 },
.divisors = { 1, 2, 4, 3, 5 },
.have_div3_pres = 1,
};
--
2.25.1
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