linux-kernel - Re: [PATCH 3/5] arm64: mte: CPU feature detection for Asymm MTE

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Message-ID: <6e6fb454-886e-95ff-fad2-d003a594acbd@arm.com>
Date:   Mon, 20 Sep 2021 16:41:56 +0100
From:   Suzuki K Poulose <suzuki.poulose@....com>
To:     Vincenzo Frascino <vincenzo.frascino@....com>,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        kasan-dev@...glegroups.com
Cc:     Andrew Morton <akpm@...ux-foundation.org>,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will@...nel.org>,
        Dmitry Vyukov <dvyukov@...gle.com>,
        Andrey Ryabinin <aryabinin@...tuozzo.com>,
        Alexander Potapenko <glider@...gle.com>,
        Marco Elver <elver@...gle.com>,
        Evgenii Stepanov <eugenis@...gle.com>,
        Branislav Rankov <Branislav.Rankov@....com>,
        Andrey Konovalov <andreyknvl@...il.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>
Subject: Re: [PATCH 3/5] arm64: mte: CPU feature detection for Asymm MTE

On 13/09/2021 09:14, Vincenzo Frascino wrote:
> Add the cpufeature entries to detect the presence of Asymmetric MTE.
> 
> Note: The tag checking mode is initialized via cpu_enable_mte() ->
> kasan_init_hw_tags() hence to enable it we require asymmetric mode
> to be at least on the boot CPU. If the boot CPU does not have it, it is
> fine for late CPUs to have it as long as the feature is not enabled
> (ARM64_CPUCAP_BOOT_CPU_FEATURE).
> 
> Cc: Will Deacon <will@...nel.org>
> Cc: Catalin Marinas <catalin.marinas@....com>
> Cc: Suzuki K Poulose <Suzuki.Poulose@....com>
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@....com>


> ---
>   arch/arm64/kernel/cpufeature.c | 10 ++++++++++
>   arch/arm64/tools/cpucaps       |  1 +
>   2 files changed, 11 insertions(+)
> 
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index f8a3067d10c6..a18774071a45 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -2317,6 +2317,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
>   		.sign = FTR_UNSIGNED,
>   		.cpu_enable = cpu_enable_mte,
>   	},
> +	{
> +		.desc = "Asymmetric Memory Tagging Extension",
> +		.capability = ARM64_MTE_ASYMM,
> +		.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,

FWIW, the selected type works for the described use case.

Reviewed-by: Suzuki K Poulose <suzuki.poulose@....com>

> +		.matches = has_cpuid_feature,
> +		.sys_reg = SYS_ID_AA64PFR1_EL1,
> +		.field_pos = ID_AA64PFR1_MTE_SHIFT,
> +		.min_field_value = ID_AA64PFR1_MTE_ASYMM,
> +		.sign = FTR_UNSIGNED,
> +	},
>   #endif /* CONFIG_ARM64_MTE */
>   	{
>   		.desc = "RCpc load-acquire (LDAPR)",
> diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
> index 49305c2e6dfd..74a569bf52d6 100644
> --- a/arch/arm64/tools/cpucaps
> +++ b/arch/arm64/tools/cpucaps
> @@ -39,6 +39,7 @@ HW_DBM
>   KVM_PROTECTED_MODE
>   MISMATCHED_CACHE_TYPE
>   MTE
> +MTE_ASYMM
>   SPECTRE_V2
>   SPECTRE_V3A
>   SPECTRE_V4
>