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Message-ID: <YUu9lKb0gdzk0ewN@pendragon.ideasonboard.com>
Date: Thu, 23 Sep 2021 02:34:44 +0300
From: Laurent Pinchart <laurent.pinchart@...asonboard.com>
To: Kieran Bingham <kieran.bingham@...asonboard.com>
Cc: Geert Uytterhoeven <geert@...der.be>,
linux-renesas-soc@...r.kernel.org,
Kieran Bingham <kieran.bingham+renesas@...asonboard.com>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Magnus Damm <magnus.damm@...il.com>,
Rob Herring <robh+dt@...nel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>,
open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 2/3] arm64: dts: renesas: r8a779a0: Add DSI encoders
Hi Kieran,
Thank you for the patch.
On Thu, Sep 02, 2021 at 12:53:29AM +0100, Kieran Bingham wrote:
> From: Kieran Bingham <kieran.bingham+renesas@...asonboard.com>
>
> Provide the two MIPI DSI encoders on the V3U and connect them to the DU
> accordingly.
>
> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@...asonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@...asonboard.com>
>
> ---
> v2
> - Fixup indentation
>
> arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 60 +++++++++++++++++++++++
> 1 file changed, 60 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> index 3241f7e7c01e..1ce9884ea527 100644
> --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> @@ -1161,12 +1161,72 @@ ports {
> port@0 {
> reg = <0>;
> du_out_dsi0: endpoint {
> + remote-endpoint = <&dsi0_in>;
> };
> };
>
> port@1 {
> reg = <1>;
> du_out_dsi1: endpoint {
> + remote-endpoint = <&dsi1_in>;
> + };
> + };
> + };
> + };
> +
> + dsi0: dsi-encoder@...80000 {
> + compatible = "renesas,r8a779a0-dsi-csi2-tx";
> + reg = <0 0xfed80000 0 0x10000>;
> + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
> + clocks = <&cpg CPG_MOD 415>,
> + <&cpg CPG_CORE R8A779A0_CLK_DSI>;
> + clock-names = "fck", "dsi";
> + resets = <&cpg 415>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi0_in: endpoint {
> + remote-endpoint = <&du_out_dsi0>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi0_out: endpoint {
> + };
> + };
> + };
> + };
> +
> + dsi1: dsi-encoder@...90000 {
> + compatible = "renesas,r8a779a0-dsi-csi2-tx";
> + reg = <0 0xfed90000 0 0x10000>;
> + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
> + clocks = <&cpg CPG_MOD 416>,
> + <&cpg CPG_CORE R8A779A0_CLK_DSI>;
> + clock-names = "fck", "dsi";
> + resets = <&cpg 416>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi1_in: endpoint {
> + remote-endpoint = <&du_out_dsi1>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi1_out: endpoint {
> };
> };
> };
--
Regards,
Laurent Pinchart
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