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Message-ID: <YUsesVeZ8PPC5iV5@zn.tnic>
Date: Wed, 22 Sep 2021 14:16:49 +0200
From: Borislav Petkov <bp@...en8.de>
To: "Luck, Tony" <tony.luck@...el.com>
Cc: Yazen Ghannam <Yazen.Ghannam@....com>, X86 ML <x86@...nel.org>,
LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 3/4] x86/mce: Get rid of msr_ops
On Mon, Sep 20, 2021 at 10:32:11AM +0200, Borislav Petkov wrote:
> but please don't make me add more helper functions. Those MSR defines
> already have "SMCA" and "IA32" in their names so that should be a good
> enough differentiation, I'd say.
I just had a better idea - it is compact but regular and one can see at
a quick glance which block is for which set of MSRs:
u32 mca_msr_reg(int bank, enum mca_msr reg)
{
if (mce_flags.smca) {
switch (reg) {
case MCA_CTL: return MSR_AMD64_SMCA_MCx_CTL(bank); break;
case MCA_ADDR: return MSR_AMD64_SMCA_MCx_ADDR(bank); break;
case MCA_MISC: return MSR_AMD64_SMCA_MCx_MISC(bank); break;
case MCA_STATUS: return MSR_AMD64_SMCA_MCx_STATUS(bank); break;
default: goto out; break;
}
}
switch (reg) {
case MCA_CTL: return MSR_IA32_MCx_CTL(bank); break;
case MCA_ADDR: return MSR_IA32_MCx_ADDR(bank); break;
case MCA_MISC: return MSR_IA32_MCx_MISC(bank); break;
case MCA_STATUS: return MSR_IA32_MCx_STATUS(bank); break;
default: goto out; break;
}
out:
WARN_ON_ONCE(1);
return 0;
}
--
Regards/Gruss,
Boris.
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