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Message-Id: <20210923201832.2553667-1-heiko@sntech.de>
Date: Thu, 23 Sep 2021 22:18:32 +0200
From: Heiko Stuebner <heiko@...ech.de>
To: linux-rockchip@...ts.infradead.org
Cc: linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
heiko@...ech.de,
Heiko Stuebner <heiko.stuebner@...obroma-systems.com>
Subject: [PATCH] arm64: dts: rockchip: add powerdomains to rk3368
From: Heiko Stuebner <heiko.stuebner@...obroma-systems.com>
Add the core io-domain node for rk3368.
Signed-off-by: Heiko Stuebner <heiko@...ech.de>
---
arch/arm64/boot/dts/rockchip/rk3368.dtsi | 173 +++++++++++++++++++++++
1 file changed, 173 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 4217897cd454..a3835dd97f99 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/power/rk3368-power.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/thermal/thermal.h>
@@ -615,6 +616,110 @@ mbox: mbox@...b0000 {
status = "disabled";
};
+ pmu: power-management@...30000 {
+ compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
+ reg = <0x0 0xff730000 0x0 0x1000>;
+
+ power: power-controller {
+ compatible = "rockchip,rk3368-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /*
+ * Note: Although SCLK_* are the working clocks
+ * of device without including on the NOC, needed for
+ * synchronous reset.
+ *
+ * The clocks on the which NOC:
+ * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
+ * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
+ * ACLK_RGA is on ACLK_RGA_NIU.
+ * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
+ *
+ * Which clock are device clocks:
+ * clocks devices
+ * *_IEP IEP:Image Enhancement Processor
+ * *_ISP ISP:Image Signal Processing
+ * *_VIP VIP:Video Input Processor
+ * *_VOP* VOP:Visual Output Processor
+ * *_RGA RGA
+ * *_EDP* EDP
+ * *_DPHY* LVDS
+ * *_HDMI HDMI
+ * *_MIPI_* MIPI
+ */
+ pd_vio@...368_PD_VIO {
+ reg = <RK3368_PD_VIO>;
+ clocks = <&cru ACLK_IEP>,
+ <&cru ACLK_ISP>,
+ <&cru ACLK_VIP>,
+ <&cru ACLK_RGA>,
+ <&cru ACLK_VOP>,
+ <&cru ACLK_VOP_IEP>,
+ <&cru DCLK_VOP>,
+ <&cru HCLK_IEP>,
+ <&cru HCLK_ISP>,
+ <&cru HCLK_RGA>,
+ <&cru HCLK_VIP>,
+ <&cru HCLK_VOP>,
+ <&cru HCLK_VIO_HDCPMMU>,
+ <&cru PCLK_EDP_CTRL>,
+ <&cru PCLK_HDMI_CTRL>,
+ <&cru PCLK_HDCP>,
+ <&cru PCLK_ISP>,
+ <&cru PCLK_VIP>,
+ <&cru PCLK_DPHYRX>,
+ <&cru PCLK_DPHYTX0>,
+ <&cru PCLK_MIPI_CSI>,
+ <&cru PCLK_MIPI_DSI0>,
+ <&cru SCLK_VOP0_PWM>,
+ <&cru SCLK_EDP_24M>,
+ <&cru SCLK_EDP>,
+ <&cru SCLK_HDCP>,
+ <&cru SCLK_ISP>,
+ <&cru SCLK_RGA>,
+ <&cru SCLK_HDMI_CEC>,
+ <&cru SCLK_HDMI_HDCP>;
+ pm_qos = <&qos_iep>,
+ <&qos_isp_r0>,
+ <&qos_isp_r1>,
+ <&qos_isp_w0>,
+ <&qos_isp_w1>,
+ <&qos_vip>,
+ <&qos_vop>,
+ <&qos_rga_r>,
+ <&qos_rga_w>;
+ };
+ /*
+ * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
+ * (video endecoder & decoder) clocks that on the
+ * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
+ */
+ pd_video@...368_PD_VIDEO {
+ reg = <RK3368_PD_VIDEO>;
+ clocks = <&cru ACLK_VIDEO>,
+ <&cru HCLK_VIDEO>,
+ <&cru SCLK_HEVC_CABAC>,
+ <&cru SCLK_HEVC_CORE>;
+ pm_qos = <&qos_hevc_r>,
+ <&qos_vpu_r>,
+ <&qos_vpu_w>;
+ };
+ /*
+ * Note: ACLK_GPU is the GPU clock,
+ * and on the ACLK_GPU_NIU (NOC).
+ */
+ pd_gpu_1@...368_PD_GPU_1 {
+ reg = <RK3368_PD_GPU_1>;
+ clocks = <&cru ACLK_GPU_CFG>,
+ <&cru ACLK_GPU_MEM>,
+ <&cru SCLK_GPU_CORE>;
+ pm_qos = <&qos_gpu>;
+ };
+ };
+ };
+
pmugrf: syscon@...38000 {
compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
reg = <0x0 0xff738000 0x0 0x1000>;
@@ -711,6 +816,7 @@ iep_mmu: iommu@...00800 {
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface";
+ power-domains = <&power RK3368_PD_VIO>;
#iommu-cells = <0>;
status = "disabled";
};
@@ -723,6 +829,7 @@ isp_mmu: iommu@...14000 {
clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
+ power-domains = <&power RK3368_PD_VIO>;
rockchip,disable-mmu-reset;
status = "disabled";
};
@@ -733,6 +840,7 @@ vop_mmu: iommu@...30300 {
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
clock-names = "aclk", "iface";
+ power-domains = <&power RK3368_PD_VIO>;
#iommu-cells = <0>;
status = "disabled";
};
@@ -759,6 +867,71 @@ vpu_mmu: iommu@...a0800 {
status = "disabled";
};
+ qos_iep: qos@...d0000 {
+ compatible = "syscon";
+ reg = <0x0 0xffad0000 0x0 0x20>;
+ };
+
+ qos_isp_r0: qos@...d0080 {
+ compatible = "syscon";
+ reg = <0x0 0xffad0080 0x0 0x20>;
+ };
+
+ qos_isp_r1: qos@...d0100 {
+ compatible = "syscon";
+ reg = <0x0 0xffad0100 0x0 0x20>;
+ };
+
+ qos_isp_w0: qos@...d0180 {
+ compatible = "syscon";
+ reg = <0x0 0xffad0180 0x0 0x20>;
+ };
+
+ qos_isp_w1: qos@...d0200 {
+ compatible = "syscon";
+ reg = <0x0 0xffad0200 0x0 0x20>;
+ };
+
+ qos_vip: qos@...d0280 {
+ compatible = "syscon";
+ reg = <0x0 0xffad0280 0x0 0x20>;
+ };
+
+ qos_vop: qos@...d0300 {
+ compatible = "syscon";
+ reg = <0x0 0xffad0300 0x0 0x20>;
+ };
+
+ qos_rga_r: qos@...d0380 {
+ compatible = "syscon";
+ reg = <0x0 0xffad0380 0x0 0x20>;
+ };
+
+ qos_rga_w: qos@...d0400 {
+ compatible = "syscon";
+ reg = <0x0 0xffad0400 0x0 0x20>;
+ };
+
+ qos_hevc_r: qos@...e0000 {
+ compatible = "syscon";
+ reg = <0x0 0xffae0000 0x0 0x20>;
+ };
+
+ qos_vpu_r: qos@...e0100 {
+ compatible = "syscon";
+ reg = <0x0 0xffae0100 0x0 0x20>;
+ };
+
+ qos_vpu_w: qos@...e0180 {
+ compatible = "syscon";
+ reg = <0x0 0xffae0180 0x0 0x20>;
+ };
+
+ qos_gpu: qos@...f0000 {
+ compatible = "syscon";
+ reg = <0x0 0xffaf0000 0x0 0x20>;
+ };
+
efuse256: efuse@...00000 {
compatible = "rockchip,rk3368-efuse";
reg = <0x0 0xffb00000 0x0 0x20>;
--
2.29.2
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