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Date: Thu, 23 Sep 2021 14:41:34 +0800 From: Chunyan Zhang <zhang.lyra@...il.com> To: Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh+dt@...nel.org> Cc: linux-clk@...r.kernel.org, devicetree@...r.kernel.org, Baolin Wang <baolin.wang7@...il.com>, Orson Zhai <orsonzhai@...il.com>, Chunyan Zhang <zhang.lyra@...il.com>, Chunyan Zhang <chunyan.zhang@...soc.com>, LKML <linux-kernel@...r.kernel.org> Subject: [PATCH v4 1/4] dt-bindings: clk: sprd: Add bindings for ums512 clock controller From: Chunyan Zhang <chunyan.zhang@...soc.com> Add a new bindings to describe ums512 clock compatible strings. Signed-off-by: Chunyan Zhang <chunyan.zhang@...soc.com> --- .../bindings/clock/sprd,ums512-clk.yaml | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml diff --git a/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml b/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml new file mode 100644 index 000000000000..992a5c150c7f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2019-2021 Unisoc Inc. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: UMS512 Clock Control Unit Device Tree Bindings + +maintainers: + - Orson Zhai <orsonzhai@...il.com> + - Baolin Wang <baolin.wang7@...il.com> + - Chunyan Zhang <zhang.lyra@...il.com> + +properties: + "#clock-cells": + const: 1 + + compatible: + enum: + - sprd,ums512-apahb-gate + - sprd,ums512-ap-clk + - sprd,ums512-aonapb-clk + - sprd,ums512-pmu-gate + - sprd,ums512-g0-pll + - sprd,ums512-g2-pll + - sprd,ums512-g3-pll + - sprd,ums512-gc-pll + - sprd,ums512-aon-gate + - sprd,ums512-audcpapb-gate + - sprd,ums512-audcpahb-gate + - sprd,ums512-gpu-clk + - sprd,ums512-mm-clk + - sprd,ums512-mm-gate-clk + - sprd,ums512-apapb-gate + + clocks: + minItems: 1 + maxItems: 4 + description: | + The input parent clock(s) phandle for this clock, only list fixed + clocks which are declared in devicetree. + + clock-names: + minItems: 1 + maxItems: 4 + items: + - const: ext-26m + - const: ext-32k + - const: ext-4m + - const: rco-100m + + reg: + maxItems: 1 + +required: + - compatible + - '#clock-cells' + - reg + +additionalProperties: false + +examples: + - | + ap_clk: clock-controller@...00000 { + compatible = "sprd,ums512-ap-clk"; + reg = <0x20200000 0x1000>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; +... -- 2.25.1
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