linux-kernel - Re: [PATCH] riscv: Add RISC-V svpbmt extension

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Message-ID: <16de95480d279b086cf0c612461e4235@mailhost.ics.forth.gr>
Date:   Thu, 23 Sep 2021 12:48:13 +0300
From:   Nick Kossifidis <mick@....forth.gr>
To:     Nick Kossifidis <mick@....forth.gr>
Cc:     Anup Patel <anup@...infault.org>, Guo Ren <guoren@...nel.org>,
        Anup Patel <anup.patel@....com>,
        Atish Patra <atish.patra@....com>,
        Palmer Dabbelt <palmerdabbelt@...gle.com>,
        Christoph Müllner <christoph.muellner@...ll.eu>,
        Philipp Tomsich <philipp.tomsich@...ll.eu>,
        Christoph Hellwig <hch@....de>,
        liush <liush@...winnertech.com>, wefu@...hat.com,
        Wei Wu (吴伟) <lazyparser@...il.com>,
        Drew Fustini <drew@...gleboard.org>,
        linux-riscv <linux-riscv@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org List" <linux-kernel@...r.kernel.org>,
        taiten.peng@...onical.com, aniket.ponkshe@...onical.com,
        Heinrich Schuchardt <heinrich.schuchardt@...onical.com>,
        gordan.markus@...onical.com, Guo Ren <guoren@...ux.alibaba.com>,
        Arnd Bergmann <arnd@...db.de>, Chen-Yu Tsai <wens@...e.org>,
        Maxime Ripard <maxime@...no.tech>,
        Daniel Lustig <dlustig@...dia.com>,
        Greg Favor <gfavor@...tanamicro.com>,
        Andrea Mondelli <andrea.mondelli@...wei.com>,
        Jonathan Behrens <behrensj@....edu>,
        Xinhaoqu <xinhaoqu@...wei.com>,
        Bill Huffman <huffman@...ence.com>,
        Allen Baum <allen.baum@...erantotech.com>,
        Josh Scheid <jscheid@...tanamicro.com>,
        Richard Trauben <rtrauben@...il.com>
Subject: Re: [PATCH] riscv: Add RISC-V svpbmt extension

Στις 2021-09-23 12:42, Nick Kossifidis έγραψε:
> Στις 2021-09-23 12:37, Anup Patel έγραψε:
>> On Thu, Sep 23, 2021 at 2:55 PM Nick Kossifidis <mick@....forth.gr> 
>> wrote:
>>> 
>>> Hello Guo,
>>> 
>>> Στις 2021-09-23 10:27, guoren@...nel.org έγραψε:
>>> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml
>>> b/Documentation/devicetree/bindings/riscv/cpus.yaml
>>> index e534f6a7cfa1..1825cd8db0de 100644
>>> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
>>> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
>>> @@ -56,7 +56,9 @@ properties:
>>>       enum:
>>>         - riscv,sv32
>>>         - riscv,sv39
>>> +      - riscv,sv39,svpbmt
>>>         - riscv,sv48
>>> +      - riscv,sv48,svpbmt
>>>         - riscv,none
>>> 
>>> Isn't svpbmt orthogonal to the mmu type ? It's a functionality that 
>>> can
>>> be present on either sv39/48/57 so why not have another "svpbmt"
>>> property directly on the cpu node ?
>> 
>> Actually, "mmu-type" would be a good place because it's page based
>> memory attribute and paging can't exist without mmu translation mode.
>> 
>> Also, "svpmbt" is indeed a CPU property so has to be feature 
>> individual
>> CPU node. Hypothetically, a heterogeneous system is possible where
>> some CPUs have "svpmbt" and some CPUs don't have "svpmbt". For
>> example, a future FUxxx SoC might have a E-core and few S-cores
>> where S-cores have Svpmbt whereas E-core does not have Svpmbt
>> because it's an embedded core.
>> 
> 
> I should say cpuX node, not the root /cpu node. We can have an svpbmt
> property in the same way we have an mmu-type property.
> 

I'm also thinking of future mmu-related extensions, e.g. what about 
svnapot ? Should we have mmu-type be riscv,sv39,svnapot and e.g. 
riscv.sv39,svpbmt,svnapot ? It'll become messy.

Regards,
Nick