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Date: Thu, 23 Sep 2021 17:46:15 +0530
From: Rajesh Patil <rajpat@...eaurora.org>
To: Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Rob Herring <robh+dt@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, rnayak@...eaurora.org,
saiprakash.ranjan@...eaurora.org, msavaliy@....qualcomm.com,
skakit@...eaurora.org, sboyd@...nel.org, mka@...omium.org,
dianders@...omium.org, Roja Rani Yarubandi <rojay@...eaurora.org>,
Rajesh Patil <rajpat@...eaurora.org>
Subject: [PATCH V10 5/8] arm64: dts: sc7280: Update QUPv3 UART5 DT node
From: Roja Rani Yarubandi <rojay@...eaurora.org>
Uart5 is treated as dedicated debug uart.Change the
compatible as "qcom,geni-uart" in SoC DT to make it generic
and later update it as "qcom,geni-debug-uart" in sc7280-idp
Add interconnects and power-domains. Split the pinctrl
functions and correct the gpio pins.
Signed-off-by: Roja Rani Yarubandi <rojay@...eaurora.org>
Signed-off-by: Rajesh Patil <rajpat@...eaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@...omium.org>
Reviewed-by: Stephen Boyd <swboyd@...omium.org>
---
Changes in V10:
- No changes
Changes in V9:
- No changes
Changes in V8:
- No changes
Changes in V7:
- As per Matthias comments,
update commit message regarding UART5 functionality
Changes in V6:
- As per Matthias' comments,
Squashed "Update QUPv3 UART5 DT node" and "Configure debug uart for sc7280-idp"
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 19 ++++++++-----------
arch/arm64/boot/dts/qcom/sc7280.dtsi | 30 +++++++++++++++++++++++++-----
2 files changed, 33 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 37b8444..cf82301 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -258,6 +258,7 @@
};
&uart5 {
+ compatible = "qcom,geni-debug-uart";
status = "okay";
};
@@ -315,18 +316,14 @@
bias-pull-up;
};
-&qup_uart5_default {
- tx {
- pins = "gpio46";
- drive-strength = <2>;
- bias-disable;
- };
+&qup_uart5_tx {
+ drive-strength = <2>;
+ bias-disable;
+};
- rx {
- pins = "gpio47";
- drive-strength = <2>;
- bias-pull-up;
- };
+&qup_uart5_rx {
+ drive-strength = <2>;
+ bias-pull-up;
};
&sdc1_on {
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 8278fd0..3254de65 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -861,13 +861,18 @@
};
uart5: serial@...000 {
- compatible = "qcom,geni-debug-uart";
+ compatible = "qcom,geni-uart";
reg = <0 0x00994000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
clock-names = "se";
pinctrl-names = "default";
- pinctrl-0 = <&qup_uart5_default>;
+ pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -2254,9 +2259,24 @@
function = "qup04";
};
- qup_uart5_default: qup-uart5-default {
- pins = "gpio46", "gpio47";
- function = "qup13";
+ qup_uart5_cts: qup-uart5-cts {
+ pins = "gpio20";
+ function = "qup05";
+ };
+
+ qup_uart5_rts: qup-uart5-rts {
+ pins = "gpio21";
+ function = "qup05";
+ };
+
+ qup_uart5_tx: qup-uart5-tx {
+ pins = "gpio22";
+ function = "qup05";
+ };
+
+ qup_uart5_rx: qup-uart5-rx {
+ pins = "gpio23";
+ function = "qup05";
};
qup_uart6_cts: qup-uart6-cts {
--
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