lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Thu, 23 Sep 2021 18:21:52 +0200 From: Konrad Dybcio <konrad.dybcio@...ainline.org> To: ~postmarketos/upstreaming@...ts.sr.ht Cc: martin.botka@...ainline.org, angelogioacchino.delregno@...ainline.org, marijn.suijten@...ainline.org, jamipkettunen@...ainline.org, Konrad Dybcio <konrad.dybcio@...ainline.org>, Andy Gross <agross@...nel.org>, Bjorn Andersson <bjorn.andersson@...aro.org>, Rob Herring <robh+dt@...nel.org>, linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org Subject: [PATCH v3 06/17] arm64: dts: qcom: sm6350: Add TLMM block node Add TLMM pinctrl node to enable referencing the SoC pins in other nodes. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...ainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@...ainline.org> --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 9934ecec1bb2..68de0beb9b01 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -404,6 +404,25 @@ pdc: interrupt-controller@...0000 { interrupt-controller; }; + tlmm: pinctrl@...0000 { + compatible = "qcom,sm6350-tlmm"; + reg = <0 0x0f100000 0 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 157>; + }; + intc: interrupt-controller@...00000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; -- 2.33.0
Powered by blists - more mailing lists