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Message-ID: <CACRpkdbUJF6VUPk9kCMPBvjeL3frJAbHq+h0-z7P-a1pSU+fiw@mail.gmail.com>
Date: Sat, 25 Sep 2021 01:48:00 +0200
From: Linus Walleij <linus.walleij@...aro.org>
To: Andrew Lunn <andrew@...n.ch>
Cc: Asmaa Mnebhi <asmaa@...dia.com>,
Andy Shevchenko <andy.shevchenko@...il.com>,
"open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
netdev <netdev@...r.kernel.org>,
linux-kernel <linux-kernel@...r.kernel.org>,
ACPI Devel Maling List <linux-acpi@...r.kernel.org>,
Jakub Kicinski <kuba@...nel.org>,
Bartosz Golaszewski <bgolaszewski@...libre.com>,
"David S. Miller" <davem@...emloft.net>,
"Rafael J. Wysocki" <rjw@...ysocki.net>,
David Thompson <davthompson@...dia.com>
Subject: Re: [PATCH v3 1/2] gpio: mlxbf2: Introduce IRQ support
On Fri, Sep 24, 2021 at 1:46 PM Andrew Lunn <andrew@...n.ch> wrote:
> > +static int
> > +mlxbf2_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
> > +{
> > + struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
> > + struct mlxbf2_gpio_context *gs = gpiochip_get_data(gc);
> > + int offset = irqd_to_hwirq(irqd);
> > + unsigned long flags;
> > + bool fall = false;
> > + bool rise = false;
> > + u32 val;
> > +
> > + switch (type & IRQ_TYPE_SENSE_MASK) {
> > + case IRQ_TYPE_EDGE_BOTH:
> > + case IRQ_TYPE_LEVEL_MASK:
> > + fall = true;
> > + rise = true;
> > + break;
> > + case IRQ_TYPE_EDGE_RISING:
> > + case IRQ_TYPE_LEVEL_HIGH:
> > + rise = true;
> > + break;
> > + case IRQ_TYPE_EDGE_FALLING:
> > + case IRQ_TYPE_LEVEL_LOW:
> > + fall = true;
> > + break;
> > + default:
> > + return -EINVAL;
> > + }
>
> I'm still not convinced this is correct. Rising edge is different to
> high. Rising edge only ever interrupts once, level keeps interrupting
> until the source is cleared. You cannot store the four different
> options in two bits.
>
> Linus, have you seen anything like this before?
No, and I agree it looks weird.
There must be some explanation, what does the datasheet say?
Yours,
Linus Walleij
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