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Message-Id: <20210925203224.10419-7-sergio.paracuellos@gmail.com> Date: Sat, 25 Sep 2021 22:32:24 +0200 From: Sergio Paracuellos <sergio.paracuellos@...il.com> To: tsbogend@...ha.franken.de Cc: robh@...nel.org, arnd@...db.de, catalin.marinas@....com, Liviu.Dudau@....com, bhelgaas@...gle.com, matthias.bgg@...il.com, gregkh@...uxfoundation.org, linux-mips@...r.kernel.org, linux-pci@...r.kernel.org, linux-staging@...ts.linux.dev, neil@...wn.name, linux-kernel@...r.kernel.org Subject: [PATCH v3 6/6] staging: mt7621-pci: properly adjust base address for the IO window The value to adjust in the bridge register RALINK_PCI_IOBASE must take into account the raw value from DT, not only the translated linux port number. As long as io_offset is zero, the two are the same, but if you were to use multiple host bridge in the system, or pick a different bus address in DT, you can have a nonzero io_offset. At this means to take into account the bus address which is used to calculate this offset, substracting it from the IO resource start address. Acked-by: Arnd Bergmann <arnd@...db.de> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@...il.com> --- drivers/staging/mt7621-pci/pci-mt7621.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index 6acfc94a16e7..503cb1fca2e0 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -482,7 +482,7 @@ static int mt7621_pcie_enable_ports(struct pci_host_bridge *host) /* Setup MEMWIN and IOWIN */ pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE); - pcie_write(pcie, entry->res->start, RALINK_PCI_IOBASE); + pcie_write(pcie, entry->res->start - entry->offset, RALINK_PCI_IOBASE); list_for_each_entry(port, &pcie->ports, list) { if (port->enabled) { -- 2.25.1
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