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Message-ID: <CAAOTY_8uRKQP5AEp6V4Ez1YZAfSYrruo5n-hG=Vp3GUPUE=sGA@mail.gmail.com> Date: Sat, 25 Sep 2021 10:11:04 +0800 From: Chun-Kuang Hu <chunkuang.hu@...nel.org> To: "jason-jh.lin" <jason-jh.lin@...iatek.com> Cc: Rob Herring <robh+dt@...nel.org>, Matthias Brugger <matthias.bgg@...il.com>, Chun-Kuang Hu <chunkuang.hu@...nel.org>, Philipp Zabel <p.zabel@...gutronix.de>, Enric Balletbo i Serra <enric.balletbo@...labora.com>, Maxime Coquelin <mcoquelin.stm32@...il.com>, David Airlie <airlied@...ux.ie>, Daniel Vetter <daniel@...ll.ch>, Alexandre Torgue <alexandre.torgue@...s.st.com>, Hsin-Yi Wang <hsinyi@...omium.org>, fshao@...omium.org, Moudy Ho <moudy.ho@...iatek.com>, roy-cw.yeh@...iatek.com, Fabien Parent <fparent@...libre.com>, Yongqiang Niu <yongqiang.niu@...iatek.com>, Nancy Lin <nancy.lin@...iatek.com>, singo.chang@...iatek.com, DTML <devicetree@...r.kernel.org>, linux-stm32@...md-mailman.stormreply.com, Linux ARM <linux-arm-kernel@...ts.infradead.org>, "moderated list:ARM/Mediatek SoC support" <linux-mediatek@...ts.infradead.org>, linux-kernel <linux-kernel@...r.kernel.org>, DRI Development <dri-devel@...ts.freedesktop.org> Subject: Re: [PATCH v11 04/16] dt-bindings: display: mediatek: dsc: add yaml for mt8195 SoC binding Hi, Jason: jason-jh.lin <jason-jh.lin@...iatek.com> 於 2021年9月21日 週二 下午11:52寫道: > > 1. Add mediatek,dsc.yaml to describe DSC module in details. > 2. Add mt8195 SoC binding to mediatek,dsc.yaml. Reviewed-by: Chun-Kuang Hu <chunkuang.hu@...nel.org> > > Signed-off-by: jason-jh.lin <jason-jh.lin@...iatek.com> > --- > .../display/mediatek/mediatek,dsc.yaml | 71 +++++++++++++++++++ > 1 file changed, 71 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml > new file mode 100644 > index 000000000000..1ec083eff824 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml > @@ -0,0 +1,71 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: mediatek display DSC controller > + > +maintainers: > + - Chun-Kuang Hu <chunkuang.hu@...nel.org> > + - Philipp Zabel <p.zabel@...gutronix.de> > + > +description: | > + The DSC standard is a specification of the algorithms used for > + compressing and decompressing image display streams, including > + the specification of the syntax and semantics of the compressed > + video bit stream. DSC is designed for real-time systems with > + real-time compression, transmission, decompression and Display. > + > +properties: > + compatible: > + oneOf: > + - items: > + - const: mediatek,mt8195-disp-dsc > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + items: > + - description: DSC Wrapper Clock > + > + power-domains: > + description: A phandle and PM domain specifier as defined by bindings of > + the power controller specified by phandle. See > + Documentation/devicetree/bindings/power/power-domain.yaml for details. > + > + mediatek,gce-client-reg: > + description: > + The register of client driver can be configured by gce with 4 arguments > + defined in this property, such as phandle of gce, subsys id, > + register offset and size. > + Each subsys id is mapping to a base address of display function blocks > + register which is defined in the gce header > + include/dt-bindings/gce/<chip>-gce.h. > + $ref: /schemas/types.yaml#/definitions/phandle-array > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + - power-domains > + - clocks > + > +additionalProperties: false > + > +examples: > + - | > + > + dsc0: disp_dsc_wrap@...09000 { > + compatible = "mediatek,mt8195-disp-dsc"; > + reg = <0 0x1c009000 0 0x1000>; > + interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > + clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; > + mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>; > + }; > -- > 2.18.0 >
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