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Date: Sun, 26 Sep 2021 15:39:41 +0800 From: Richard Zhu <hongxing.zhu@....com> To: l.stach@...gutronix.de, kishon@...com, vkoul@...nel.org, robh@...nel.org, galak@...nel.crashing.org, shawnguo@...nel.org Cc: linux-phy@...ts.infradead.org, devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, kernel@...gutronix.de, linux-imx@....com, Richard Zhu <hongxing.zhu@....com> Subject: [PATCH v2 2/4] dt-bindings: phy: add imx8 pcie phy driver support Add dt-binding for the standalone i.MX8 PCIe PHY driver. Signed-off-by: Richard Zhu <hongxing.zhu@....com> --- .../bindings/phy/fsl,imx8-pcie-phy.yaml | 67 +++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml new file mode 100644 index 000000000000..fd08897fef82 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8 SoC series PCIe PHY Device Tree Bindings + +maintainers: + - Richard Zhu <hongxing.zhu@....com> + +properties: + "#phy-cells": + const: 0 + + compatible: + enum: + - fsl,imx8mm-pcie-phy + + reg: + maxItems: 1 + + clocks: + items: + - description: PHY module clock + + clock-names: + items: + - const: phy + + fsl,refclk-pad-mode: + description: | + Specifies the mode of the refclk pad used. It can be NO_USED(PHY + refclock is derived from SoC internal source), INPUT(PHY refclock + is provided externally via the refclk pad) or OUTPUT(PHY refclock + is derived from SoC internal source and provided on the refclk pad). + Refer include/dt-bindings/phy/phy-imx8-pcie.h for the constants + to be used. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2 ] + +required: + - "#phy-cells" + - compatible + - reg + - clocks + - clock-names + - fsl,refclk-pad-mode + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx8mm-clock.h> + + pcie_phy: pcie-phy@...00000 { + compatible = "fsl,imx8mm-pcie-phy"; + reg = <0x32f00000 0x10000>; + clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; + clock-names = "phy"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; + assigned-clock-rates = <100000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>; + fsl,refclk-pad-mode = <1>; + #phy-cells = <0>; + }; +... -- 2.25.1
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