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Message-ID: <87lf3jaubj.ffs@tglx>
Date:   Sun, 26 Sep 2021 23:41:20 +0200
From:   Thomas Gleixner <tglx@...utronix.de>
To:     shruthi.sanil@...el.com, daniel.lezcano@...aro.org,
        robh+dt@...nel.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org
Cc:     andriy.shevchenko@...ux.intel.com, kris.pan@...ux.intel.com,
        mgross@...ux.intel.com, srikanth.thokala@...el.com,
        lakshmi.bai.raja.subramanian@...el.com,
        mallikarjunappa.sangannavar@...el.com, shruthi.sanil@...el.com
Subject: Re: [PATCH v6 2/2] clocksource: Add Intel Keem Bay timer support

On Tue, Sep 07 2021 at 00:06, shruthi sanil wrote:
> +
> +/* Provides a unique ID for each timer */
> +static DEFINE_IDA(keembay_timer_ida);

> +
> +	timer_id = ida_alloc(&keembay_timer_ida, GFP_KERNEL);
> +	if (timer_id < 0) {
> +		ret = timer_id;
> +		goto err_keembay_ce_to_free;
> +	}

May I ask what the purpose of the IDA, which is backed by a full blown
xarray, is here?

AFAICT all you want is a unique number for the timer name for up to 8
timers.

> +	timer_name = kasprintf(GFP_KERNEL, "keembay_timer%d", timer_id);

So what's wrong about:

static unsigned int keembay_timer_id;

	timer_name = kasprintf(GFP_KERNEL, "keembay_timer%d", keembay_timer_id++);

Hmm?

> +
> +	clockevents_config_and_register(&keembay_ce_to->clkevt,
> +					timer_of_rate(keembay_ce_to),
> +					1,
> +					U32_MAX);

Aside of that what's the point of registering more than one of those
timers as clock event? The core will only use one and the rest is just
going to use memory for no value.

Thanks,

        tglx

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