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Message-Id: <20210926224058.1252-35-digetx@gmail.com>
Date: Mon, 27 Sep 2021 01:40:57 +0300
From: Dmitry Osipenko <digetx@...il.com>
To: Thierry Reding <thierry.reding@...il.com>,
Jonathan Hunter <jonathanh@...dia.com>,
Ulf Hansson <ulf.hansson@...aro.org>,
Viresh Kumar <vireshk@...nel.org>,
Stephen Boyd <sboyd@...nel.org>,
Peter De Schrijver <pdeschrijver@...dia.com>,
Mikko Perttunen <mperttunen@...dia.com>,
Peter Chen <peter.chen@...nel.org>,
Lee Jones <lee.jones@...aro.org>,
Uwe Kleine-König
<u.kleine-koenig@...gutronix.de>, Nishanth Menon <nm@...com>,
Adrian Hunter <adrian.hunter@...el.com>,
Michael Turquette <mturquette@...libre.com>
Cc: linux-kernel@...r.kernel.org, linux-tegra@...r.kernel.org,
linux-pm@...r.kernel.org, linux-usb@...r.kernel.org,
linux-staging@...ts.linux.dev, linux-pwm@...r.kernel.org,
linux-mmc@...r.kernel.org, dri-devel@...ts.freedesktop.org,
devicetree@...r.kernel.org, linux-clk@...r.kernel.org,
Mark Brown <broonie@...nel.org>,
Vignesh Raghavendra <vigneshr@...com>,
Richard Weinberger <richard@....at>,
Miquel Raynal <miquel.raynal@...tlin.com>,
Lucas Stach <dev@...xeye.de>, Stefan Agner <stefan@...er.ch>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
David Heidelberg <david@...t.cz>
Subject: [PATCH v13 34/35] ARM: tegra: Add Memory Client resets to Tegra30 GR2D, GR3D and Host1x
Memory access must be blocked before hardware reset is asserted and before
power is gated, otherwise a serious hardware fault is inevitable. Add
reset for memory clients to the GR2D, GR3D and Host1x nodes.
Tested-by: Peter Geis <pgwipeout@...il.com> # Ouya T30
Tested-by: Matt Merhar <mattmerhar@...tonmail.com> # Ouya T30
Signed-off-by: Dmitry Osipenko <digetx@...il.com>
---
arch/arm/boot/dts/tegra30.dtsi | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index c8130f8f680e..09cb1ab75312 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -123,8 +123,8 @@ host1x@...00000 {
interrupt-names = "syncpt", "host1x";
clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
clock-names = "host1x";
- resets = <&tegra_car 28>;
- reset-names = "host1x";
+ resets = <&tegra_car 28>, <&mc TEGRA30_MC_RESET_HC>;
+ reset-names = "host1x", "mc";
iommus = <&mc TEGRA_SWGROUP_HC>;
operating-points-v2 = <&host1x_dvfs_opp_table>;
power-domains = <&pd_heg>;
@@ -190,8 +190,8 @@ gr2d@...40000 {
reg = <0x54140000 0x00040000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_GR2D>;
- resets = <&tegra_car 21>;
- reset-names = "2d";
+ resets = <&tegra_car 21>, <&mc TEGRA30_MC_RESET_2D>;
+ reset-names = "2d", "mc";
operating-points-v2 = <&gr2d_dvfs_opp_table>;
power-domains = <&pd_heg>;
@@ -205,8 +205,10 @@ gr3d@...80000 {
<&tegra_car TEGRA30_CLK_GR3D2>;
clock-names = "3d", "3d2";
resets = <&tegra_car 24>,
- <&tegra_car 98>;
- reset-names = "3d", "3d2";
+ <&tegra_car 98>,
+ <&mc TEGRA30_MC_RESET_3D>,
+ <&mc TEGRA30_MC_RESET_3D2>;
+ reset-names = "3d", "3d2", "mc", "mc2";
operating-points-v2 = <&gr3d_dvfs_opp_table>;
power-domains = <&pd_3d0>, <&pd_3d1>;
power-domain-names = "3d0", "3d1";
--
2.32.0
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