linux-kernel - [PATCH 5.14 043/162] platform/x86: amd-pmc: Increase the response register timeout

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Message-Id: <20210927170234.998866332@linuxfoundation.org>
Date:   Mon, 27 Sep 2021 19:01:29 +0200
From:   Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To:     linux-kernel@...r.kernel.org
Cc:     Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        stable@...r.kernel.org, stable@...nel.org,
        Julian Sikorski <belegdol@...il.com>,
        Mario Limonciello <mario.limonciello@....com>,
        Shyam Sundar S K <Shyam-sundar.S-k@....com>,
        Hans de Goede <hdegoede@...hat.com>
Subject: [PATCH 5.14 043/162] platform/x86: amd-pmc: Increase the response register timeout

From: Mario Limonciello <mario.limonciello@....com>

commit 3c3c8e88c8712bfe06cd10d7ca77a94a33610cd6 upstream.

There have been reports of approximately a 0.9%-1.7% failure rate in SMU
communication timeouts with s0i3 entry on some OEM designs.  Currently
the design in amd-pmc is to try every 100us for up to 20ms.

However the GPU driver which also communicates with the SMU using a
mailbox register which the driver polls every 1us for up to 2000ms.
In the GPU driver this was increased by commit 055162645a40 ("drm/amd/pm:
increase time out value when sending msg to SMU")

Increase the maximum timeout used by amd-pmc to 2000ms to match this
behavior.  This has been shown to improve the stability for machines
that randomly have failures.

Cc: stable@...nel.org
Reported-by: Julian Sikorski <belegdol@...il.com>
BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1629
Signed-off-by: Mario Limonciello <mario.limonciello@....com>
Acked-by: Shyam Sundar S K <Shyam-sundar.S-k@....com>
Link: https://lore.kernel.org/r/20210914020115.655-1-mario.limonciello@amd.com
Signed-off-by: Hans de Goede <hdegoede@...hat.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
---
 drivers/platform/x86/amd-pmc.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- a/drivers/platform/x86/amd-pmc.c
+++ b/drivers/platform/x86/amd-pmc.c
@@ -71,7 +71,7 @@
 #define AMD_CPU_ID_YC			0x14B5
 
 #define PMC_MSG_DELAY_MIN_US		100
-#define RESPONSE_REGISTER_LOOP_MAX	200
+#define RESPONSE_REGISTER_LOOP_MAX	20000
 
 #define SOC_SUBSYSTEM_IP_MAX	12
 #define DELAY_MIN_US		2000