linux-kernel - Re: [PATCH v2 4/5] ASoC: codecs: tx-macro: Update tx default values

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Mon, 27 Sep 2021 11:42:52 +0100
From:   Srinivas Kandagatla <srinivas.kandagatla@...aro.org>
To:     Srinivasa Rao Mandadapu <srivasam@...eaurora.org>,
        agross@...nel.org, bjorn.andersson@...aro.org, lgirdwood@...il.com,
        broonie@...nel.org, robh+dt@...nel.org, plai@...eaurora.org,
        bgoswami@...eaurora.org, perex@...ex.cz, tiwai@...e.com,
        rohitkr@...eaurora.org, linux-arm-msm@...r.kernel.org,
        alsa-devel@...a-project.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, swboyd@...omium.org,
        judyhsiao@...omium.org
Cc:     Venkata Prasad Potturu <potturu@...eaurora.org>
Subject: Re: [PATCH v2 4/5] ASoC: codecs: tx-macro: Update tx default values



On 22/09/2021 13:31, Srinivasa Rao Mandadapu wrote:
> Update mic control register default values to hardware reset values
> 
> Fixes: c39667ddcfc5 (ASoC: codecs: lpass-tx-macro: add support for lpass tx macro)
> 
> Signed-off-by: Venkata Prasad Potturu <potturu@...eaurora.org>
> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@...eaurora.org>
> ---
>   sound/soc/codecs/lpass-tx-macro.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/sound/soc/codecs/lpass-tx-macro.c b/sound/soc/codecs/lpass-tx-macro.c
> index e980b2e..66c39fb 100644
> --- a/sound/soc/codecs/lpass-tx-macro.c
> +++ b/sound/soc/codecs/lpass-tx-macro.c
> @@ -279,7 +279,7 @@ static const struct reg_default tx_defaults[] = {
>   	{ CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 0x00},
>   	{ CDC_TX_TOP_CSR_TOP_CFG0, 0x00},
>   	{ CDC_TX_TOP_CSR_ANC_CFG, 0x00},
> -	{ CDC_TX_TOP_CSR_SWR_CTRL, 0x00},
> +	{ CDC_TX_TOP_CSR_SWR_CTRL, 0x60},

This does not make sense as this register only has one bit to control.
Why do we even need to change this, can you please explain what happens 
if we do not change this?

>   	{ CDC_TX_TOP_CSR_FREQ_MCLK, 0x00},
>   	{ CDC_TX_TOP_CSR_DEBUG_BUS, 0x00},
>   	{ CDC_TX_TOP_CSR_DEBUG_EN, 0x00},
> @@ -290,8 +290,8 @@ static const struct reg_default tx_defaults[] = {
>   	{ CDC_TX_TOP_CSR_SWR_DMIC1_CTL, 0x00},
>   	{ CDC_TX_TOP_CSR_SWR_DMIC2_CTL, 0x00},
>   	{ CDC_TX_TOP_CSR_SWR_DMIC3_CTL, 0x00},
> -	{ CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0x00},
> -	{ CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0x00},
> +	{ CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0x0E},
> +	{ CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0x0E},

These two registers should have default value of 0x06 as this has only 
one clk selection field with bits 2:1.

-srini


>   	{ CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00},
>   	{ CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00},
>   	{ CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00},
>