linux-kernel - Re: [PATCH v2 2/2] arm64: dts: qcom: sm8250: Add Coresight support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <8ff1838f88670cc401a35dc43cc43feb@codeaurora.org>
Date:   Mon, 27 Sep 2021 09:56:38 +0530
From:   Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>
To:     Tao Zhang <quic_taozha@...cinc.com>
Cc:     Mathieu Poirier <mathieu.poirier@...aro.org>,
        Suzuki K Poulose <suzuki.poulose@....com>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Andy Gross <agross@...nel.org>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, Mike Leach <mike.leach@...aro.org>,
        Leo Yan <leo.yan@...aro.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        coresight@...ts.linaro.org, linux-arm-kernel@...ts.infradead.org,
        Tingwei Zhang <quic_tingweiz@...cinc.com>,
        Mao Jinlong <quic_jinlmao@...cinc.com>,
        Yuanfang Zhang <quic_yuanfang@...cinc.com>
Subject: Re: [PATCH v2 2/2] arm64: dts: qcom: sm8250: Add Coresight support

Hi Tao,

On 2021-09-27 08:13, Tao Zhang wrote:
> Add the basic coresight components found on Qualcomm SM8250 Soc. The
> basic coresight components include ETF, ETMs,STM and the related
> funnels.
> ETM verification and use of Coresight components need Coresight
> support in this device tree. Since the ETR sink needs SMMU support,
> and SMMU has not been enabled on RB5. ETR is not added to this patch,
> and it will be added once SMMU is enabled on RB5. ETF sink has been
> added to the device tree for RB5.
> 

RB5 board is based on SM8250 SoC and coresight is a SoC level IP (won't
change per board, although can be disabled per board) and as such these
coresight dt nodes should be in sm8250.dtsi (please look at other 
examples
in SM8150/SC7180/SC7280).

Similarly SMMU support is not per board (RB5), it's already supported
for SM8250 long time back (check for apps_smmu in sm8250.dtsi), so you
can add ETR support when you post v3 (note this patch which you have
posted should have been v3 as v2 was your previous version). You can 
just
post one patch with the coresight dt entries as the ETM driver patch is
already queued by Suzuki in coresight tree. You can use the following 
qcom
tree [1] when posting DT for QCOM devices (branch: for-next), also 
please
remember to *sort the nodes by address*.

[1] 
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git/?h=for-next

Thanks,
Sai

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a 
member
of Code Aurora Forum, hosted by The Linux Foundation