linux-kernel - [PATCH v1 1/2] dt-bindings: memory: tegra20: emc: Document optional LPDDR properties

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Wed, 29 Sep 2021 23:03:04 +0300
From:   Dmitry Osipenko <digetx@...il.com>
To:     Thierry Reding <thierry.reding@...il.com>,
        Jonathan Hunter <jonathanh@...dia.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
        Rob Herring <robh+dt@...nel.org>
Cc:     devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-tegra@...r.kernel.org
Subject: [PATCH v1 1/2] dt-bindings: memory: tegra20: emc: Document optional LPDDR properties

Some Tegra20 boards don't use RAM code for the memory chip identification
and the identity information should read out from LPDDR chip in this case.
Document new optional generic LPDDR properties that will be used for the
memory chip identification if RAM code isn't provided.

Signed-off-by: Dmitry Osipenko <digetx@...il.com>
---
 .../nvidia,tegra20-emc.yaml                   | 43 +++++++++++++++++--
 1 file changed, 40 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml
index cac6842dc8f1..6d01b1bf6304 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml
@@ -158,6 +158,46 @@ patternProperties:
         description:
           Value of RAM_CODE this timing set is used for.
 
+      jedec,lpddr-manufacturer-id:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description:
+          Unique manufacturer ID of SDRAM chip this timing set is used for.
+          See MR5 description in JEDEC LPDDR2 specification (JESD209-2).
+
+      jedec,lpddr-revision-id1:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description:
+          Revision 1 value of SDRAM chip this timing set is used for.
+          See MR6 description in chip vendor specification.
+
+      jedec,lpddr-revision-id2:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description:
+          Revision 2 value of SDRAM chip this timing set is used for.
+          See MR7 description in chip vendor specification.
+
+      jedec,lpddr-density-mbits:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description:
+          Density in megabits of SDRAM chip this timing set is used for.
+          See MR8 description in JEDEC LPDDR2 specification.
+
+      jedec,lpddr-io-width-bits:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description:
+          IO bus width in bits of SDRAM chip this timing set is used for.
+          See MR8 description in JEDEC LPDDR2 specification.
+
+      jedec,lpddr-type:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description:
+          LPDDR type which corresponds to a number of words SDRAM pre-fetches
+          per column request that this timing set is used for.
+          See MR8 description in JEDEC LPDDR2 specification.
+        enum:
+          - 4 # S4 (4 words prefetch architecture)
+          - 2 # S2 (2 words prefetch architecture)
+
       "#address-cells":
         const: 1
 
@@ -168,9 +208,6 @@ patternProperties:
       "^emc-table@[0-9]+$":
         $ref: "#/$defs/emc-table"
 
-    required:
-      - nvidia,ram-code
-
     additionalProperties: false
 
 required:
-- 
2.32.0