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Message-ID: <202109302046.uPMqjGop-lkp@intel.com>
Date: Thu, 30 Sep 2021 15:47:31 +0300
From: Dan Carpenter <dan.carpenter@...cle.com>
To: kbuild@...ts.01.org, Yash Shah <yash.shah@...ive.com>
Cc: lkp@...el.com, kbuild-all@...ts.01.org,
linux-kernel@...r.kernel.org,
Palmer Dabbelt <palmerdabbelt@...gle.com>
Subject: [kbuild] drivers/soc/sifive/sifive_l2_cache.c:235 sifive_l2_init()
warn: 'l2_base' not released on lines: 215.
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 02d5e016800d082058b3d3b7c3ede136cdc6ddcb
commit: 507308b8ccc90d37b07bfca8ffe130435d6b354f RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive FU740
config: riscv-randconfig-m031-20210930 (attached as .config)
compiler: riscv64-linux-gcc (GCC) 11.2.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@...el.com>
Reported-by: Dan Carpenter <dan.carpenter@...cle.com>
smatch warnings:
drivers/soc/sifive/sifive_l2_cache.c:235 sifive_l2_init() warn: 'l2_base' not released on lines: 215.
vim +/l2_base +235 drivers/soc/sifive/sifive_l2_cache.c
bf6df5dd25b7440 arch/riscv/mm/sifive_l2_cache.c Paul Walmsley 2019-10-17 195 static int __init sifive_l2_init(void)
a967a289f169695 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 196 {
a967a289f169695 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 197 struct device_node *np;
a967a289f169695 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 198 struct resource res;
507308b8ccc90d3 drivers/soc/sifive/sifive_l2_cache.c Yash Shah 2020-12-10 199 int i, rc, intr_num;
a967a289f169695 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 200
a967a289f169695 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 201 np = of_find_matching_node(NULL, sifive_l2_ids);
a967a289f169695 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 202 if (!np)
a967a289f169695 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 203 return -ENODEV;
a967a289f169695 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 204
a967a289f169695 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 205 if (of_address_to_resource(np, 0, &res))
a967a289f169695 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 206 return -ENODEV;
a967a289f169695 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 207
a967a289f169695 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 208 l2_base = ioremap(res.start, resource_size(&res));
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
a967a289f169695 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 209 if (!l2_base)
a967a289f169695 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 210 return -ENOMEM;
a967a289f169695 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 211
507308b8ccc90d3 drivers/soc/sifive/sifive_l2_cache.c Yash Shah 2020-12-10 212 intr_num = of_property_count_u32_elems(np, "interrupts");
507308b8ccc90d3 drivers/soc/sifive/sifive_l2_cache.c Yash Shah 2020-12-10 213 if (!intr_num) {
507308b8ccc90d3 drivers/soc/sifive/sifive_l2_cache.c Yash Shah 2020-12-10 214 pr_err("L2CACHE: no interrupts property\n");
507308b8ccc90d3 drivers/soc/sifive/sifive_l2_cache.c Yash Shah 2020-12-10 215 return -ENODEV;
No clean up here. iounmap().
rc = -ENODEV;
goto unmap;
507308b8ccc90d3 drivers/soc/sifive/sifive_l2_cache.c Yash Shah 2020-12-10 216 }
507308b8ccc90d3 drivers/soc/sifive/sifive_l2_cache.c Yash Shah 2020-12-10 217
507308b8ccc90d3 drivers/soc/sifive/sifive_l2_cache.c Yash Shah 2020-12-10 218 for (i = 0; i < intr_num; i++) {
a967a289f169695 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 219 g_irq[i] = irq_of_parse_and_map(np, i);
a967a289f169695 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 220 rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
a967a289f169695 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 221 if (rc) {
a967a289f169695 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 222 pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
a967a289f169695 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 223 return rc;
Or here. Release the previous IRQs and iounmap(). Yes, this probably
won't boot but we may as well do it correctly because it's less hassle
than debating endlessly whenever someone runs a static checker on the
code.
goto release_irqs;
...
return 0;
release_irqs:
while (--i >= 0)
release_irq();
unmap:
iounmap();
return rc;
a967a289f169695 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 224 }
a967a289f169695 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 225 }
a967a289f169695 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 226
a967a289f169695 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 227 l2_config_read();
a967a289f169695 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 228
4a3a37331248d85 drivers/soc/sifive/sifive_l2_cache.c Yash Shah 2020-02-20 229 l2_cache_ops.get_priv_group = l2_get_priv_group;
4a3a37331248d85 drivers/soc/sifive/sifive_l2_cache.c Yash Shah 2020-02-20 230 riscv_set_cacheinfo_ops(&l2_cache_ops);
4a3a37331248d85 drivers/soc/sifive/sifive_l2_cache.c Yash Shah 2020-02-20 231
a967a289f169695 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 232 #ifdef CONFIG_DEBUG_FS
a967a289f169695 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 233 setup_sifive_debug();
a967a289f169695 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 234 #endif
a967a289f169695 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 @235 return 0;
---
0-DAY CI Kernel Test Service, Intel Corporation
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