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Message-ID: <06a40d0d-da39-ba0b-e932-d4435c0735d3@linaro.org>
Date: Sat, 2 Oct 2021 00:09:15 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Sireesh Kodali <sireeshkodali1@...il.com>,
phone-devel@...r.kernel.org, ~postmarketos/upstreaming@...ts.sr.ht,
dri-devel@...ts.freedesktop.org, freedreno@...ts.freedesktop.org,
devicetree@...r.kernel.org, linux-arm-msm@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: Vladimir Lypak <vladimir.lypak@...il.com>,
Rob Clark <robdclark@...il.com>, Sean Paul <sean@...rly.run>,
David Airlie <airlied@...ux.ie>,
Daniel Vetter <daniel@...ll.ch>,
Konrad Dybcio <konrad.dybcio@...ainline.org>,
Abhinav Kumar <abhinavk@...eaurora.org>,
James Willcox <jwillcox@...areup.com>
Subject: Re: [PATCH v3 3/3] drm/msm/mdp5: Add configuration for MDP v1.16
On 28/09/2021 16:19, Sireesh Kodali wrote:
> From: Vladimir Lypak <vladimir.lypak@...il.com>
>
> MDP version v1.16 is almost identical to v1.15 with most significant
> difference being presence of second DSI interface. MDP v1.16 is found on
> SoCs such as MSM8x53, SDM450, SDM632 (All with Adreno 506).
>
> Signed-off-by: Vladimir Lypak <vladimir.lypak@...il.com>
> Signed-off-by: Sireesh Kodali <sireeshkodali1@...il.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
> ---
> drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 89 ++++++++++++++++++++++++
> 1 file changed, 89 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
> index 9741544ffc35..0d28c8ff4009 100644
> --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
> +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
> @@ -752,6 +752,94 @@ const struct mdp5_cfg_hw msm8x76_config = {
> .max_clk = 360000000,
> };
>
> +static const struct mdp5_cfg_hw msm8x53_config = {
> + .name = "msm8x53",
> + .mdp = {
> + .count = 1,
> + .caps = MDP_CAP_CDM |
> + MDP_CAP_SRC_SPLIT,
> + },
> + .ctl = {
> + .count = 3,
> + .base = { 0x01000, 0x01200, 0x01400 },
> + .flush_hw_mask = 0xffffffff,
> + },
> + .pipe_vig = {
> + .count = 1,
> + .base = { 0x04000 },
> + .caps = MDP_PIPE_CAP_HFLIP |
> + MDP_PIPE_CAP_VFLIP |
> + MDP_PIPE_CAP_SCALE |
> + MDP_PIPE_CAP_CSC |
> + MDP_PIPE_CAP_DECIMATION |
> + MDP_PIPE_CAP_SW_PIX_EXT |
> + 0,
> + },
> + .pipe_rgb = {
> + .count = 2,
> + .base = { 0x14000, 0x16000 },
> + .caps = MDP_PIPE_CAP_HFLIP |
> + MDP_PIPE_CAP_VFLIP |
> + MDP_PIPE_CAP_DECIMATION |
> + MDP_PIPE_CAP_SW_PIX_EXT |
> + 0,
> + },
> + .pipe_dma = {
> + .count = 1,
> + .base = { 0x24000 },
> + .caps = MDP_PIPE_CAP_HFLIP |
> + MDP_PIPE_CAP_VFLIP |
> + MDP_PIPE_CAP_SW_PIX_EXT |
> + 0,
> + },
> + .pipe_cursor = {
> + .count = 1,
> + .base = { 0x34000 },
> + .caps = MDP_PIPE_CAP_HFLIP |
> + MDP_PIPE_CAP_VFLIP |
> + MDP_PIPE_CAP_SW_PIX_EXT |
> + MDP_PIPE_CAP_CURSOR |
> + 0,
> + },
> +
> + .lm = {
> + .count = 3,
> + .base = { 0x44000, 0x45000 },
> + .instances = {
> + { .id = 0, .pp = 0, .dspp = 0,
> + .caps = MDP_LM_CAP_DISPLAY |
> + MDP_LM_CAP_PAIR },
> + { .id = 1, .pp = 1, .dspp = -1,
> + .caps = MDP_LM_CAP_DISPLAY },
> + },
> + .nb_stages = 5,
> + .max_width = 2048,
> + .max_height = 0xFFFF,
> + },
> + .dspp = {
> + .count = 1,
> + .base = { 0x54000 },
> +
> + },
> + .pp = {
> + .count = 2,
> + .base = { 0x70000, 0x70800 },
> + },
> + .cdm = {
> + .count = 1,
> + .base = { 0x79200 },
> + },
> + .intf = {
> + .base = { 0x6a000, 0x6a800, 0x6b000 },
> + .connect = {
> + [0] = INTF_DISABLED,
> + [1] = INTF_DSI,
> + [2] = INTF_DSI,
> + },
> + },
> + .max_clk = 400000000,
> +};
> +
> static const struct mdp5_cfg_hw msm8917_config = {
> .name = "msm8917",
> .mdp = {
> @@ -1151,6 +1239,7 @@ static const struct mdp5_cfg_handler cfg_handlers_v1[] = {
> { .revision = 7, .config = { .hw = &msm8x96_config } },
> { .revision = 11, .config = { .hw = &msm8x76_config } },
> { .revision = 15, .config = { .hw = &msm8917_config } },
> + { .revision = 16, .config = { .hw = &msm8x53_config } },
> };
>
> static const struct mdp5_cfg_handler cfg_handlers_v3[] = {
>
--
With best wishes
Dmitry
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