linux-kernel - Re: [PATCH 0/4] spi: cadence-quadspi: Add Xilinx Versal OSPI support

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Date:   Sat,  2 Oct 2021 01:16:23 +0100
From:   Mark Brown <broonie@...nel.org>
To:     Michal Simek <michal.simek@...inx.com>,
        Rob Herring <robh+dt@...nel.org>,
        Pratyush Yadav <p.yadav@...com>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@...inx.com>
Cc:     Mark Brown <broonie@...nel.org>, git@...inx.com,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        saikrishna12468@...il.com, linux-spi@...r.kernel.org,
        Arnd Bergmann <arnd@...db.de>,
        Nobuhiro Iwamatsu <iwamatsu@...auri.org>,
        linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 0/4] spi: cadence-quadspi: Add Xilinx Versal OSPI support

On Fri, 24 Sep 2021 15:37:07 +0530, Sai Krishna Potthuri wrote:
> Add Octal SPI(OSPI) controller support for Xilinx Versal SoC.
> Update the binding to add Xilinx Versal compatible string, also add
> 'power-domains' property and made as required for Xilinx Versal SoCs.
> Add API in xilinx firmware for configuring OSPI Mux, which is
> required to change the interface to OSPI. Xilinx Versal SoC
> has external DMA support, so by using the OSPI MUX selection, interface
> to the OSPI will be selected (either DMA interface or AXI slave interface).
> Xilinx Versal OSPI external DMA:
> Xilinx Versal OSPI DMA module is integrated to the Cadence OSPI Controller
> with the DMA write channel. Cadence OSPI Controller which reads the data
> from the Flash and stores in its internal SRAM and Xilinx Versal OSPI DMA
> which reads the data from the SRAM in the Cadence OSPI Controller using
> the DMA SRC channel and then the DMA DST channel initiates a write DMA
> transfer into the destined address location.
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next

Thanks!

[1/4] firmware: xilinx: Add OSPI Mux selection support
      commit: 74e78adc6ccf6c3b53939788cf0c49f54db70731
[2/4] dt-bindings: spi: cadence-quadspi: Add support for Xilinx Versal OSPI
      commit: 8db76cfae1004f5476d9c35670f0a0f084c6b73f
[3/4] spi: cadence-quadspi: Add OSPI support for Xilinx Versal SoC
      commit: 09e393e3f13970f194f7ed9a93140a8601225b46
[4/4] spi: cadence-quadspi: Add Xilinx Versal external DMA support
      commit: 1a6f854f7daab100ff0a94d31f35a387b462b4d1

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark