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Message-ID: <CAE-0n50_Qtz4OfZ9og8BWUZRe8DYRPnoSkOSAHgzTd3bpA32cw@mail.gmail.com>
Date: Mon, 4 Oct 2021 14:30:16 -0400
From: Stephen Boyd <swboyd@...omium.org>
To: Rakesh Pillai <pillair@...eaurora.org>, agross@...nel.org,
bjorn.andersson@...aro.org, mathieu.poirier@...aro.org,
ohad@...ery.com, p.zabel@...gutronix.de, robh+dt@...nel.org
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, sibis@...eaurora.org,
mpubbise@...eaurora.org, kuabhs@...omium.org
Subject: Re: [PATCH v6 1/3] dt-bindings: remoteproc: qcom: adsp: Convert
binding to YAML
Quoting Rakesh Pillai (2021-10-03 23:48:51)
> diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-cdsp-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-cdsp-pil.yaml
> new file mode 100644
> index 0000000..b698bb7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-cdsp-pil.yaml
> @@ -0,0 +1,167 @@
[...]
> +
> + qcom,smem-state-names:
> + $ref: /schemas/types.yaml#/definitions/string
> + description: The names of the state bits used for SMP2P output
> + items:
> + - const: stop
> +
> +required:
> + - compatible
> + - reg
> + - interrupts-extended
> + - interrupt-names
> + - clocks
> + - clock-names
> + - power-domains
> + - reset
> + - reset-names
> + - qcom,halt-regs
> + - memory-region
> + - qcom,smem-states
> + - qcom,smem-state-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/qcom,gcc-qcs404.h>
> + #include <dt-bindings/clock/qcom,turingcc-qcs404.h>
> + remoteproc@...000 {
> + compatible = "qcom,qcs404-cdsp-pas";
> + reg = <0x00b00000 0x4040>;
> +
> + interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
> + <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> + <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> + <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> + <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "wdog", "fatal", "ready",
> + "handover", "stop-ack";
> +
> + clocks = <&xo_board>,
> + <&gcc GCC_CDSP_CFG_AHB_CLK>,
> + <&gcc GCC_CDSP_TBU_CLK>,
> + <&gcc GCC_BIMC_CDSP_CLK>,
> + <&turingcc TURING_WRAPPER_AON_CLK>,
> + <&turingcc TURING_Q6SS_AHBS_AON_CLK>,
> + <&turingcc TURING_Q6SS_AHBM_AON_CLK>,
> + <&turingcc TURING_Q6SS_Q6_AXIM_CLK>;
> + clock-names = "xo",
> + "sway",
> + "tbu",
> + "bimc",
> + "ahb_aon",
> + "q6ss_slave",
> + "q6ss_master",
> + "q6_axim";
> +
> + resets = <&gcc GCC_CDSP_RESTART>;
> + reset-names = "restart";
> +
> + qcom,halt-regs = <&tcsr 0x19004>;
> +
> + memory-region = <&cdsp_fw_mem>;
> +
> + qcom,smem-states = <&cdsp_smp2p_out 0>;
> + qcom,smem-state-names = "stop";
> +
> + glink-edge {
Where is glink-edge documented as a property?
> + interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
> +
> + qcom,remote-pid = <5>;
> + mboxes = <&apcs_glb 12>;
> +
> + label = "cdsp";
It would be good to have these properties defined as well and maybe
include the common schema for a glink edge that way.
> + };
> + };
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