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Message-Id: <1633376488-545-4-git-send-email-pmaliset@codeaurora.org>
Date: Tue, 5 Oct 2021 01:11:26 +0530
From: Prasad Malisetty <pmaliset@...eaurora.org>
To: agross@...nel.org, bjorn.andersson@...aro.org, bhelgaas@...gle.com,
robh+dt@...nel.org, swboyd@...omium.org, lorenzo.pieralisi@....com,
svarbanov@...sol.com
Cc: devicetree@...r.kernel.org, linux-arm-msm@...r.kernel.org,
linux-usb@...r.kernel.org, linux-kernel@...r.kernel.org,
dianders@...omium.org, mka@...omium.org, vbadigan@...eaurora.org,
sallenki@...eaurora.org, manivannan.sadhasivam@...aro.org,
linux-pci@...r.kernel.org,
Prasad Malisetty <pmaliset@...eaurora.org>
Subject: [PATCH v10 3/5] arm64: dts: qcom: sc7280: Add PCIe nodes for IDP board
Enable PCIe controller and PHY for sc7280 IDP board.
Add specific NVMe GPIO entries for SKU1 and SKU2 support.
Signed-off-by: Prasad Malisetty <pmaliset@...eaurora.org>
---
arch/arm64/boot/dts/qcom/sc7280-idp.dts | 8 +++++
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 51 ++++++++++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/sc7280-idp2.dts | 8 +++++
3 files changed, 67 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
index 64fc22a..5b1c96b 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
@@ -61,6 +61,14 @@
modem-init;
};
+&nvme_pwren_pin {
+ pins = "gpio19";
+};
+
+&nvme_3v3_regulator {
+ gpio = <&tlmm 19 GPIO_ACTIVE_HIGH>;
+};
+
&pmk8350_vadc {
pmr735a_die_temp {
reg = <PMR735A_ADC7_DIE_TEMP>;
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 272d5ca..b416f3d 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -31,6 +31,18 @@
linux,can-disable;
};
};
+
+ nvme_3v3_regulator: nvme-3v3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "VLDO_3V3";
+
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&nvme_pwren_pin>;
+ };
};
/*
@@ -272,6 +284,23 @@
modem-init;
};
+&pcie1 {
+ status = "okay";
+ perst-gpio = <&tlmm 2 GPIO_ACTIVE_LOW>;
+
+ vddpe-3v3-supply = <&nvme_3v3_regulator>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_default_state>, <&pcie1_reset_n>, <&pcie1_wake_n>;
+};
+
+&pcie1_phy {
+ status = "okay";
+
+ vdda-phy-supply = <&vreg_l10c_0p8>;
+ vdda-pll-supply = <&vreg_l6b_1p2>;
+};
+
&pmk8350_vadc {
pmk8350_die_temp {
reg = <PMK8350_ADC7_DIE_TEMP>;
@@ -462,6 +491,28 @@
};
&tlmm {
+ nvme_pwren_pin: nvme-pwren-pin {
+ function = "gpio";
+ bias-pull-up;
+ };
+
+ pcie1_reset_n: pcie1-reset-n {
+ pins = "gpio2";
+ function = "gpio";
+
+ drive-strength = <16>;
+ output-low;
+ bias-disable;
+ };
+
+ pcie1_wake_n: pcie1-wake-n {
+ pins = "gpio3";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
qup_uart7_sleep_cts: qup-uart7-sleep-cts {
pins = "gpio28";
function = "gpio";
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp2.dts b/arch/arm64/boot/dts/qcom/sc7280-idp2.dts
index 1fc2add..f2722c0 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp2.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp2.dts
@@ -21,3 +21,11 @@
stdout-path = "serial0:115200n8";
};
};
+
+&nvme_pwren_pin {
+ pins = "gpio51";
+};
+
+&nvme_3v3_regulator {
+ gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>;
+};
--
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