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Message-ID: <CAAOTY_8H=TE8574xB3FFcGVgN_fTb_83+FT8ei1CDuB4k4-Oew@mail.gmail.com>
Date: Tue, 5 Oct 2021 07:53:04 +0800
From: Chun-Kuang Hu <chunkuang.hu@...nel.org>
To: Jitao Shi <jitao.shi@...iatek.com>
Cc: Chun-Kuang Hu <chunkuang.hu@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Matthias Brugger <matthias.bgg@...il.com>,
Daniel Vetter <daniel@...ll.ch>,
David Airlie <airlied@...ux.ie>,
DRI Development <dri-devel@...ts.freedesktop.org>,
linux-kernel <linux-kernel@...r.kernel.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@...ts.infradead.org>,
Linux ARM <linux-arm-kernel@...ts.infradead.org>,
CK Hu <ck.hu@...iatek.com>, stonea168@....com,
huijuan.xie@...iatek.com, Rex-BC Chen <rex-bc.chen@...iatek.com>,
shuijing.li@...iatek.com
Subject: Re: [PATCH v7 1/3] drm/dsi: transer dsi hs packet aligned
Hi, Jitao:
Jitao Shi <jitao.shi@...iatek.com> 於 2021年9月16日 週四 上午6:31寫道:
>
> Some DSI devices reqire the hs packet starting and ending
> at same time on all dsi lanes. So use a flag to those devices.
>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@...nel.org>
> Signed-off-by: Jitao Shi <jitao.shi@...iatek.com>
> ---
> include/drm/drm_mipi_dsi.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
> index af7ba8071eb0..8e8563792682 100644
> --- a/include/drm/drm_mipi_dsi.h
> +++ b/include/drm/drm_mipi_dsi.h
> @@ -177,6 +177,7 @@ struct mipi_dsi_device_info {
> * @lp_rate: maximum lane frequency for low power mode in hertz, this should
> * be set to the real limits of the hardware, zero is only accepted for
> * legacy drivers
> + * @hs_packet_end_aligned: transfer dsi hs packet ending aligned
> */
> struct mipi_dsi_device {
> struct mipi_dsi_host *host;
> @@ -189,6 +190,7 @@ struct mipi_dsi_device {
> unsigned long mode_flags;
> unsigned long hs_rate;
> unsigned long lp_rate;
> + bool hs_packet_end_aligned;
> };
>
> #define MIPI_DSI_MODULE_PREFIX "mipi-dsi:"
> --
> 2.25.1
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