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Date:   Tue, 5 Oct 2021 17:53:04 +0200
From:   Geert Uytterhoeven <geert@...ux-m68k.org>
To:     Nikita Yushchenko <nikita.yoush@...entembedded.com>
Cc:     Geert Uytterhoeven <geert+renesas@...der.be>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
        linux-clk <linux-clk@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Andrey Gusakov <andrey.gusakov@...entembedded.com>
Subject: Re: [PATCH] clk: renesas: r8a779[56]x: add MLP clock

Hi Nikita,

On Wed, Sep 29, 2021 at 11:35 PM Nikita Yushchenko
<nikita.yoush@...entembedded.com> wrote:
> From: Andrey Gusakov <andrey.gusakov@...entembedded.com>
>
> Add clocks for MLP module on Renesas H3 and M3.
>
> Signed-off-by: Andrey Gusakov <andrey.gusakov@...entembedded.com>
> Signed-off-by: Nikita Yushchenko <nikita.yoush@...entembedded.com>

Thanks for your patch!

> --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
> @@ -229,6 +229,7 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
>         DEF_MOD("lvds",                  727,   R8A7795_CLK_S0D4),
>         DEF_MOD("hdmi1",                 728,   R8A7795_CLK_HDMI),
>         DEF_MOD("hdmi0",                 729,   R8A7795_CLK_HDMI),
> +       DEF_MOD("mlp",                   802,   R8A7795_CLK_S2D1),
>         DEF_MOD("vin7",                  804,   R8A7795_CLK_S0D2),
>         DEF_MOD("vin6",                  805,   R8A7795_CLK_S0D2),
>         DEF_MOD("vin5",                  806,   R8A7795_CLK_S0D2),
> diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
> index 41593c126faf..9c22977e42c2 100644
> --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
> @@ -207,6 +207,7 @@ static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = {
>         DEF_MOD("du0",                   724,   R8A7796_CLK_S2D1),
>         DEF_MOD("lvds",                  727,   R8A7796_CLK_S2D1),
>         DEF_MOD("hdmi0",                 729,   R8A7796_CLK_HDMI),
> +       DEF_MOD("mlp",                   802,   R8A7796_CLK_S2D1),
>         DEF_MOD("vin7",                  804,   R8A7796_CLK_S0D2),
>         DEF_MOD("vin6",                  805,   R8A7796_CLK_S0D2),
>         DEF_MOD("vin5",                  806,   R8A7796_CLK_S0D2),
> diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
> index bc1be8bcbbe4..52c5da26b756 100644
> --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
> @@ -205,6 +205,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
>         DEF_MOD("lvds",                 727,    R8A77965_CLK_S2D1),
>         DEF_MOD("hdmi0",                729,    R8A77965_CLK_HDMI),
>
> +       DEF_MOD("mlp",                  802,    R8A77965_CLK_S2D1),
>         DEF_MOD("vin7",                 804,    R8A77965_CLK_S0D2),
>         DEF_MOD("vin6",                 805,    R8A77965_CLK_S0D2),
>         DEF_MOD("vin5",                 806,    R8A77965_CLK_S0D2),

These additions look fine to me.  I'm only wondering about the
actual parent clocks, which are not well-documented in the Hardware
User's Manual.
It does say that MLP uses the Audio main bus (AXI).
The related AUDIO-DMAC uses S1D2, which runs at 266 MHz, while S2D1
runs at 400 MHz?

BTW, do you plan to enable full support for MLP in the upstream kernel?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

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