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Date: Tue, 5 Oct 2021 14:48:37 +0530
From: Kajol Jain <kjain@...ux.ibm.com>
To: mpe@...erman.id.au, linuxppc-dev@...ts.ozlabs.org,
linux-kernel@...r.kernel.org, peterz@...radead.org,
mingo@...hat.com, acme@...nel.org, jolsa@...nel.org,
namhyung@...nel.org, ak@...ux.intel.com
Cc: linux-perf-users@...r.kernel.org, maddy@...ux.ibm.com,
atrajeev@...ux.vnet.ibm.com, rnsastry@...ux.ibm.com,
yao.jin@...ux.intel.com, ast@...nel.org, daniel@...earbox.net,
songliubraving@...com, kan.liang@...ux.intel.com,
mark.rutland@....com, alexander.shishkin@...ux.intel.com,
paulus@...ba.org, kjain@...ux.ibm.com
Subject: [PATCH 4/4] powerpc/perf: Fix data source encodings for L2.1 and L3.1 accesses
Fix the data source encodings to represent L2.1/L3.1(another core's
L2/L3 on the same chip) accesses properly for power10 and older
plaforms.
Add new macros(LEVEL/REM) which can be used to add mem_lvl_num and remote
field data inside perf_mem_data_src structure.
Result in power9 system with patch changes:
localhost:~/linux/tools/perf # ./perf mem report | grep Remote
0.01% 1 236 Remote core, same chip L3 or L3 hit [.] 0x0000000000002dd0 producer_consumer [.] 0x00007fffadd4cc10
anon HitM N/A No N/A 0 0
0.01% 1 208 Remote core, same chip L3 or L3 hit [.] 0x0000000000002dd0 producer_consumer [.] 0x00007fff9dd33710
anon HitM N/A No N/A 0 0
0.00% 1 176 Remote core, same chip L3 or L3 hit [.] 0x0000000000002dd0 producer_consumer [.] 0x00007fff9b22c290
anon HitM N/A No N/A 0 0
Fixes: 79e96f8f930d ("powerpc/perf: Export memory hierarchy info to user
space")
Signed-off-by: Kajol Jain <kjain@...ux.ibm.com>
---
arch/powerpc/perf/isa207-common.c | 26 +++++++++++++++++++++-----
arch/powerpc/perf/isa207-common.h | 2 ++
2 files changed, 23 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c
index f92bf5f6b74f..7ea873ab2e6f 100644
--- a/arch/powerpc/perf/isa207-common.c
+++ b/arch/powerpc/perf/isa207-common.c
@@ -238,11 +238,27 @@ static inline u64 isa207_find_source(u64 idx, u32 sub_idx)
ret |= P(SNOOP, HIT);
break;
case 5:
- ret = PH(LVL, REM_CCE1);
- if ((sub_idx == 0) || (sub_idx == 2) || (sub_idx == 4))
- ret |= P(SNOOP, HIT);
- else if ((sub_idx == 1) || (sub_idx == 3) || (sub_idx == 5))
- ret |= P(SNOOP, HITM);
+ if (cpu_has_feature(CPU_FTR_ARCH_31)) {
+ ret = REM | P(HOPS, 0);
+
+ if (sub_idx == 0 || sub_idx == 4)
+ ret |= PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT);
+ else if (sub_idx == 1 || sub_idx == 5)
+ ret |= PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HITM);
+ else if (sub_idx == 2 || sub_idx == 6)
+ ret |= PH(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT);
+ else if (sub_idx == 3 || sub_idx == 7)
+ ret |= PH(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
+ } else {
+ if (sub_idx == 0)
+ ret = PH(LVL, L2) | LEVEL(L2) | REM | P(SNOOP, HIT) | P(HOPS, 0);
+ else if (sub_idx == 1)
+ ret = PH(LVL, L2) | LEVEL(L2) | REM | P(SNOOP, HITM) | P(HOPS, 0);
+ else if (sub_idx == 2 || sub_idx == 4)
+ ret = PH(LVL, L3) | LEVEL(L3) | REM | P(SNOOP, HIT) | P(HOPS, 0);
+ else if (sub_idx == 3 || sub_idx == 5)
+ ret = PH(LVL, L3) | LEVEL(L3) | REM | P(SNOOP, HITM) | P(HOPS, 0);
+ }
break;
case 6:
ret = PH(LVL, REM_CCE2);
diff --git a/arch/powerpc/perf/isa207-common.h b/arch/powerpc/perf/isa207-common.h
index 4a2cbc3dc047..ff122603989b 100644
--- a/arch/powerpc/perf/isa207-common.h
+++ b/arch/powerpc/perf/isa207-common.h
@@ -273,6 +273,8 @@
#define P(a, b) PERF_MEM_S(a, b)
#define PH(a, b) (P(LVL, HIT) | P(a, b))
#define PM(a, b) (P(LVL, MISS) | P(a, b))
+#define LEVEL(x) P(LVLNUM, x)
+#define REM P(REMOTE, REMOTE)
int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp, u64 event_config1);
int isa207_compute_mmcr(u64 event[], int n_ev,
--
2.26.2
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