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Date:   Tue, 5 Oct 2021 12:05:23 +0200
From:   Borislav Petkov <>
To:     Ser Olmy <>
Cc:     "" <>,
        x86-ml <>
Subject: Re: [x86] Kernel v5.14 series panic on Celeron Mendocino CPU

On Mon, Oct 04, 2021 at 06:17:42PM +0000, Ser Olmy wrote:
> On Monday, October 4th, 2021 at 7:59 PM, Borislav Petkov <> wrote:
> >
> > I'm assuming your CPU cannot do 64-bit mode?
> Correct, it's an old Socket 370 Celeron

Ok, thanks for the info.

On your next reply, can you please hit the "reply-to-all" button so that
I can get your reply and not have to go fish it out of the lkml flood? I
would've easily missed it if tglx didn't point me to it.

In any case, your CPU is too old for me to even find such a box and your
.config boots fine in qemu so I guess we'll have to debug it.

Can you apply the diff below on your 5.14.9 kernel, boot with it and
send full dmesg again?


diff --git a/arch/x86/kernel/fpu/init.c b/arch/x86/kernel/fpu/init.c
index 64e29927cc32..5c6c11f831ed 100644
--- a/arch/x86/kernel/fpu/init.c
+++ b/arch/x86/kernel/fpu/init.c
@@ -112,7 +112,11 @@ static void __init fpu__init_system_mxcsr(void)
 		if (mask == 0)
 			mask = 0x0000ffbf;
 	mxcsr_feature_mask &= mask;
+	pr_info("%s: mxcsr_feature_mask: 0x%x, mask: 0x%x\n",
+		__func__, mxcsr_feature_mask, mask);
diff --git a/arch/x86/kernel/fpu/signal.c b/arch/x86/kernel/fpu/signal.c
index 445c57c9c539..808a0ff85141 100644
--- a/arch/x86/kernel/fpu/signal.c
+++ b/arch/x86/kernel/fpu/signal.c
@@ -380,8 +380,11 @@ static int __fpu_restore_sig(void __user *buf, void __user *buf_fx,
 			return -EFAULT;
 		/* Reject invalid MXCSR values. */
-		if (fpu->state.fxsave.mxcsr & ~mxcsr_feature_mask)
+		if (fpu->state.fxsave.mxcsr & ~mxcsr_feature_mask) {
+			WARN_ONCE(1, "fpu->state.fxsave.mxcsr: 0x%x, mxcsr_feature_mask: 0x%x\n",
+				  fpu->state.fxsave.mxcsr, mxcsr_feature_mask);
 			return -EINVAL;
+		}
 		/* Enforce XFEATURE_MASK_FPSSE when XSAVE is enabled */
 		if (use_xsave())


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