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Date:   Tue,  5 Oct 2021 15:49:00 +0200
From:   Martin Kepplinger <martin.kepplinger@...i.sm>
To:     martin.kepplinger@...i.sm
Cc:     devicetree@...r.kernel.org, festevam@...il.com,
        kernel@...gutronix.de, kernel@...i.sm,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        phone-devel@...r.kernel.org, robh@...nel.org, shawnguo@...nel.org,
        Angus Ainslie <angus@...ea.ca>
Subject: [PATCH v2 5/7] arm64: dts: imx8mq-librem5: add power sequencing for M.2 cards

From: Angus Ainslie <angus@...ea.ca>

Some wifi cards need reset asserted until after the power supplies
have been enabled.

So wire up the W_DISABLE signal for the SDIO port (WIFI_REG_ON net) and
the BT_REG_ON net to use it for power sequencing.

Signed-off-by: Angus Ainslie <angus@...ea.ca>
Signed-off-by: Martin Kepplinger <martin.kepplinger@...i.sm>
---
 .../boot/dts/freescale/imx8mq-librem5.dtsi    | 23 +++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
index 7a09312f31c4..396eb4434229 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
@@ -198,6 +198,14 @@ simple-audio-card,codec {
 		};
 	};
 
+	usdhc2_pwrseq: pwrseq {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_bt>, <&pinctrl_wifi_disable>;
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>,
+			      <&gpio4 29 GPIO_ACTIVE_HIGH>;
+	};
+
 	bm818_codec: sound-wwan-codec {
 		compatible = "broadmobi,bm818", "option,gtm601";
 		#sound-dai-cells = <0>;
@@ -312,6 +320,13 @@ MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14	0x83
 		>;
 	};
 
+	pinctrl_bt: btgrp {
+		fsl,pins = <
+			/* BT_REG_ON */
+			MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25	0x83
+		>;
+	};
+
 	pinctrl_charger_in: chargeringrp {
 		fsl,pins = <
 			/* CHRG_INT */
@@ -643,6 +658,13 @@ MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0xc1
 		>;
 	};
 
+	pinctrl_wifi_disable: wifidisablegrp {
+		fsl,pins = <
+			/* WIFI_REG_ON */
+			MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29	0x83
+		>;
+	};
+
 	pinctrl_wifi_pwr: wifipwrgrp {
 		fsl,pins = <
 			/* WIFI3V3_EN */
@@ -1212,6 +1234,7 @@ &usdhc2 {
 	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 	bus-width = <4>;
 	vmmc-supply = <&reg_wifi_3v3>;
+	mmc-pwrseq = <&usdhc2_pwrseq>;
 	post-power-on-delay-ms = <1000>;
 	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 	disable-wp;
-- 
2.30.2

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