linux-kernel - Re: [PATCH 2/4] perf: Add mem_hops field in perf_mem_data

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Message-ID: <be06c316-d257-4175-7b33-43220014d234@linux.ibm.com>
Date:   Wed, 6 Oct 2021 12:08:40 +0530
From:   kajoljain <kjain@...ux.ibm.com>
To:     Peter Zijlstra <peterz@...radead.org>
Cc:     mpe@...erman.id.au, linuxppc-dev@...ts.ozlabs.org,
        linux-kernel@...r.kernel.org, mingo@...hat.com, acme@...nel.org,
        jolsa@...nel.org, namhyung@...nel.org, ak@...ux.intel.com,
        linux-perf-users@...r.kernel.org, maddy@...ux.ibm.com,
        atrajeev@...ux.vnet.ibm.com, rnsastry@...ux.ibm.com,
        yao.jin@...ux.intel.com, ast@...nel.org, daniel@...earbox.net,
        songliubraving@...com, kan.liang@...ux.intel.com,
        mark.rutland@....com, alexander.shishkin@...ux.intel.com,
        paulus@...ba.org
Subject: Re: [PATCH 2/4] perf: Add mem_hops field in perf_mem_data_src
 structure



On 10/6/21 1:50 AM, Peter Zijlstra wrote:
> On Tue, Oct 05, 2021 at 02:48:35PM +0530, Kajol Jain wrote:
>> Going forward, future generation systems can have more hierarchy
>> within the chip/package level but currently we don't have any data source
>> encoding field in perf, which can be used to represent this level of data.
>>
>> Add a new field called 'mem_hops' in the perf_mem_data_src structure
>> which can be used to represent intra-chip/package or inter-chip/off-package
>> details. This field is of size 3 bits where PERF_MEM_HOPS_{NA, 0..6} value
>> can be used to present different hop levels data.
>>
>> Also add corresponding macros to define mem_hop field values
>> and shift value.
>>
>> Currently we define macro for HOPS_0 which corresponds
>> to data coming from another core but same chip.
>>
>> For ex: Encodings for mem_hops fields with L2 cache:
>>
>> L2			- local L2
>> L2 | REMOTE | HOPS_0	- remote core, same chip L2
> 
> Can we do s/chip/node/ ? Hops are something NUMA related, while chips
> come in a bag or something :-)

Hi Peter,
  Sure, I will make this change in next version of this patch-set.

Thanks,
Kajol Jain

> 
>> +/* hop level */
>> +#define PERF_MEM_HOPS_0		0x01 /* remote core, same chip */
>> +/* 2-7 available */
>> +#define PERF_MEM_HOPS_SHIFT	43