| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <1633600649-7164-5-git-send-email-mkshah@codeaurora.org>
Date: Thu, 7 Oct 2021 15:27:28 +0530
From: Maulik Shah <mkshah@...eaurora.org>
To: swboyd@...omium.org, mka@...omium.org, evgreen@...omium.org,
bjorn.andersson@...aro.org
Cc: linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
agross@...nel.org, dianders@...omium.org, linux@...ck-us.net,
rnayak@...eaurora.org, lsrao@...eaurora.org,
Maulik Shah <mkshah@...eaurora.org>, devicetree@...r.kernel.org
Subject: [PATCH v11 4/5] arm64: dts: qcom: Enable RPMh Sleep stats
Add device node for Sleep stats driver which provides various
low power mode stats on sc7180, sc7280, sm8150, sm8250 and sm8350.
Also update the reg size of aoss_qmp device to 0x400.
Cc: devicetree@...r.kernel.org
Signed-off-by: Maulik Shah <mkshah@...eaurora.org>
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 7 ++++++-
arch/arm64/boot/dts/qcom/sc7280.dtsi | 7 ++++++-
arch/arm64/boot/dts/qcom/sm8150.dtsi | 7 ++++++-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 7 ++++++-
arch/arm64/boot/dts/qcom/sm8350.dtsi | 7 ++++++-
5 files changed, 30 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index f10217c..e849810 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -3219,13 +3219,18 @@
aoss_qmp: power-controller@...0000 {
compatible = "qcom,sc7180-aoss-qmp";
- reg = <0 0x0c300000 0 0x100000>;
+ reg = <0 0x0c300000 0 0x400>;
interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apss_shared 0>;
#clock-cells = <0>;
};
+ sram@...0000 {
+ compatible = "qcom,rpmh-sleep-stats";
+ reg = <0 0x0c3f0000 0 0x400>;
+ };
+
spmi_bus: spmi@...0000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0 0x0c440000 0 0x1100>,
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 39635da..b21c55a 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2637,7 +2637,7 @@
aoss_qmp: power-controller@...0000 {
compatible = "qcom,sc7280-aoss-qmp";
- reg = <0 0x0c300000 0 0x100000>;
+ reg = <0 0x0c300000 0 0x400>;
interrupts-extended = <&ipcc IPCC_CLIENT_AOP
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
@@ -2647,6 +2647,11 @@
#clock-cells = <0>;
};
+ sram@...0000 {
+ compatible = "qcom,rpmh-sleep-stats";
+ reg = <0 0x0c3f0000 0 0x400>;
+ };
+
spmi_bus: spmi@...0000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0 0x0c440000 0 0x1100>,
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 8a03569..bde3776 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -3170,13 +3170,18 @@
aoss_qmp: power-controller@...0000 {
compatible = "qcom,sm8150-aoss-qmp";
- reg = <0x0 0x0c300000 0x0 0x100000>;
+ reg = <0x0 0x0c300000 0x0 0x400>;
interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apss_shared 0>;
#clock-cells = <0>;
};
+ sram@...0000 {
+ compatible = "qcom,rpmh-sleep-stats";
+ reg = <0 0x0c3f0000 0 0x400>;
+ };
+
tsens0: thermal-sensor@...3000 {
compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
reg = <0 0x0c263000 0 0x1ff>, /* TM */
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 2796b27..a815101 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2899,7 +2899,7 @@
aoss_qmp: power-controller@...0000 {
compatible = "qcom,sm8250-aoss-qmp";
- reg = <0 0x0c300000 0 0x100000>;
+ reg = <0 0x0c300000 0 0x400>;
interrupts-extended = <&ipcc IPCC_CLIENT_AOP
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
@@ -2909,6 +2909,11 @@
#clock-cells = <0>;
};
+ sram@...0000 {
+ compatible = "qcom,rpmh-sleep-stats";
+ reg = <0 0x0c3f0000 0 0x400>;
+ };
+
spmi_bus: spmi@...0000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0 0x0c440000 0x0 0x0001100>,
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 6c83cd5..778a4b6 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -788,7 +788,7 @@
aoss_qmp: power-controller@...0000 {
compatible = "qcom,sm8350-aoss-qmp";
- reg = <0 0x0c300000 0 0x100000>;
+ reg = <0 0x0c300000 0 0x400>;
interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
@@ -796,6 +796,11 @@
#clock-cells = <0>;
};
+ sram@...0000 {
+ compatible = "qcom,rpmh-sleep-stats";
+ reg = <0 0x0c3f0000 0 0x400>;
+ };
+
spmi_bus: spmi@...0000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0 0xc440000 0x0 0x1100>,
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Powered by blists - more mailing lists