Message-Id: <20211007123632.697666-1-anup.patel@wdc.com>
Date:   Thu,  7 Oct 2021 18:06:22 +0530
From:   Anup Patel <anup.patel@....com>
To:     Palmer Dabbelt <palmer@...belt.com>,
        Palmer Dabbelt <palmerdabbelt@...gle.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Marc Zyngier <maz@...nel.org>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        Rob Herring <robh+dt@...nel.org>
Cc:     Atish Patra <atish.patra@....com>,
        Alistair Francis <Alistair.Francis@....com>,
        Anup Patel <anup@...infault.org>,
        linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, Anup Patel <anup.patel@....com>
Subject: [RFC PATCH v4 00/10] Linux RISC-V ACLINT Support

Most of the existing RISC-V platforms use SiFive CLINT to provide M-level
timer and IPI support whereas S-level uses SBI calls for timer and IPI
support. Also, the SiFive CLINT device is a single device providing both
timer and IPI functionality so RISC-V platforms can't partially implement
SiFive CLINT device and provide alternate mechanism for timer and IPI.

The RISC-V Advacned Core Local Interruptor (ACLINT) tries to address the
limitations of the SiFive CLINT by:
1) Taking modular approach and defining timer and IPI functionality as
   separate devices so that RISC-V platforms can include only required
   devices
2) Providing dedicated MMIO device for S-level IPIs so that SBI calls
   can be avoided for IPIs in Linux RISC-V
3) Allowing multiple instances of timer and IPI devices for a
   multi-socket (or multi-die) NUMA systems

The RISC-V ACLINT specification is backward compatible to the SiFive CLINT
so existing RISC-V platforms with SiFive CLINT are already compliant.

Latest RISC-V ACLINT specification (is stable and will be frozen soon)
can be found at:
https://github.com/riscv/riscv-aclint/releases/download/v1.0-rc2/riscv-aclint-1.0-rc2.pdf

This series adds RISC-V ACLINT support and can be found in the
riscv_aclint_v4 branch at: https://github.com/avpatel/linux

This series is tested on QEMU virt machine with both MMU and NoMMU
Linux RISC-V kernel.

Changes since v3:
 - Dropped PATCH which was updating SiFive CLINT DT bindings
 - Updated MTIMER, MSWI, and SSWI DT bindings to mandate a implmentation
   specific compatible strings
 - Added MTIMER and MSWI implementation specific compatible strings for
   existing platforms with SiFive CLINT
 - Call aclint_swi_init() from CLINT timer driver in PATCH9 when we are
   dealing with SiFive CLINT device

Changes since v2:
 - Addresed Rob's comments on [M|S]SWI DT bindings
 - Dropped PATCH2 because it was not a required change
 - Addressed Marc's comments on ACLINT SWI driver added by PATCH7
 - Added a separate PATCH6 to update SiFive CLINT DT bindings

Changes since v1:
 - Added a new PATCH3 to treat IPIs as normal Linux IRQs for RISC-V kernel
 - New SBI IPI call based irqchip driver in PATCH3 which is only initialized
   by riscv_ipi_setup() when no Linux IRQ numbers are available for IPIs
 - Moved DT bindings patches before corresponding driver patches
 - Implemented ACLINT SWI driver as a irqchip driver in PATCH7
 - Minor nit fixes pointed by Bin Meng

Anup Patel (10):
  RISC-V: Clear SIP bit only when using SBI IPI operations
  RISC-V: Treat IPIs as normal Linux IRQs
  RISC-V: Allow marking IPIs as suitable for remote FENCEs
  RISC-V: Use IPIs for remote TLB flush when possible
  dt-bindings: interrupt-controller: Add ACLINT MSWI and SSWI bindings
  irqchip: Add ACLINT software interrupt driver
  RISC-V: Select ACLINT SWI driver for virt machine
  dt-bindings: timer: Add ACLINT MTIMER bindings
  clocksource: clint: Add support for ACLINT MTIMER device
  MAINTAINERS: Add entry for RISC-V ACLINT drivers

 .../riscv,aclint-swi.yaml                     |  97 ++++++
 .../bindings/timer/riscv,aclint-mtimer.yaml   |  67 +++++
 MAINTAINERS                                   |  10 +
 arch/riscv/Kconfig                            |   1 +
 arch/riscv/Kconfig.socs                       |   1 +
 arch/riscv/include/asm/sbi.h                  |   2 +
 arch/riscv/include/asm/smp.h                  |  49 ++-
 arch/riscv/kernel/Makefile                    |   1 +
 arch/riscv/kernel/cpu-hotplug.c               |   3 +-
 arch/riscv/kernel/irq.c                       |   3 +-
 arch/riscv/kernel/sbi-ipi.c                   | 218 ++++++++++++++
 arch/riscv/kernel/sbi.c                       |  15 -
 arch/riscv/kernel/smp.c                       | 167 ++++++-----
 arch/riscv/kernel/smpboot.c                   |   5 +-
 arch/riscv/mm/tlbflush.c                      |  91 ++++--
 drivers/clocksource/timer-clint.c             |  80 ++---
 drivers/irqchip/Kconfig                       |   9 +
 drivers/irqchip/Makefile                      |   1 +
 drivers/irqchip/irq-riscv-aclint-swi.c        | 282 ++++++++++++++++++
 drivers/irqchip/irq-riscv-intc.c              |  55 ++--
 include/linux/irqchip/irq-riscv-aclint-swi.h  |  19 ++
 21 files changed, 974 insertions(+), 202 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
 create mode 100644 Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
 create mode 100644 arch/riscv/kernel/sbi-ipi.c
 create mode 100644 drivers/irqchip/irq-riscv-aclint-swi.c
 create mode 100644 include/linux/irqchip/irq-riscv-aclint-swi.h

-- 
2.25.1

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