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Message-Id: <20211008205628.3073014-1-georgedanielmangum@gmail.com>
Date: Fri, 8 Oct 2021 16:56:25 -0400
From: hasheddan <georgedanielmangum@...il.com>
To: unlisted-recipients:; (no To-header on input)
Cc: georgedanielmangum@...il.com,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Atish Patra <atish.patra@....com>,
Peter Zijlstra <peterz@...radead.org>,
Kefeng Wang <wangkefeng.wang@...wei.com>,
Will Deacon <will@...nel.org>,
Thomas Gleixner <tglx@...utronix.de>,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [PATCH] riscv: cacheinfo: fix typo of homogenous
Updates 'homonogenous' to 'homogenous' in comment.
Signed-off-by: hasheddan <georgedanielmangum@...il.com>
---
arch/riscv/kernel/cacheinfo.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
index 90deabfe63ea..ff98546b1152 100644
--- a/arch/riscv/kernel/cacheinfo.c
+++ b/arch/riscv/kernel/cacheinfo.c
@@ -29,7 +29,7 @@ static struct cacheinfo *get_cacheinfo(u32 level, enum cache_type type)
/*
* Using raw_smp_processor_id() elides a preemptability check, but this
* is really indicative of a larger problem: the cacheinfo UABI assumes
- * that cores have a homonogenous view of the cache hierarchy. That
+ * that cores have a homogenous view of the cache hierarchy. That
* happens to be the case for the current set of RISC-V systems, but
* likely won't be true in general. Since there's no way to provide
* correct information for these systems via the current UABI we're
--
2.25.1
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